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Old 27th December 2009, 10:34 PM   #11
JensH is offline JensH  Denmark
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I agree with godfrey. You should probably try to simulate it without feedback first. The DC working point can be a bit tricky to get right though.

I see a similar issue when I simulate a KGSS headphone amplifier I am currently working on. With the loop closed, I get a small peak in the frequency response at around 3MHz and a positive phase with a peak of +50 degrees at around 6MHz. When I simulate it open loop I get a relatively low gain a these frequencies, but with a lot of phase shift, leading to an almost positive feedback.
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Old 27th December 2009, 11:10 PM   #12
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Also, try making R5 about 10k (9.4k would be optimal but I don't think that's a resistor value...). This way the current through Q11 and Q10 will be equal, making that arrangement more linear.

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Old 27th December 2009, 11:34 PM   #13
danhard is offline danhard  Czech Republic
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Alternate analysis is only valid for stable circuits.
This is oscillator.
Positive shift is a sign of.
Try to use the Boode criterium of stability.
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Old 28th December 2009, 01:57 AM   #14
danhard is offline danhard  Czech Republic
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And above all does not work dc.
I2 - 2mA
I1 - 10mA
R5 - 4k
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Old 28th December 2009, 04:09 PM   #15
sigpl is offline sigpl  Europe
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Noted myself that adding a load on the output totally changed the situation. Now the transfer is more what one would expect.

Listening to some of your advices, and removing one current amplifier, the result is much better. Posting a new circuit, the frequency transfer and the step response of the current thru Q6 (with resistor R4 this corresponds to a near 20 V step in 20ns). Unfortunately the step is not that good after the FETs, but that is due to them solely (or?).

This rises some new questions. In the LTSpice model, the MOSFETs draw a lot of current on the gate (up to 0.5mA), not DC but when applying the signal source. How come? Does anyone know how where to find appropriate models for say 2SK1058 and 2SJ162? How do I add such a model ?
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File Type: png step.PNG (3.9 KB, 67 views)
File Type: png circuit.PNG (30.0 KB, 57 views)
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Old 28th December 2009, 04:22 PM   #16
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Try IRF610 and IRF9610. If you don't have them I can give you models if you need them.

Also, you may want to put a diode in series with Q5's emitter. Normally Q3 has 0V Vcb which is unhealthy for a BJT.

The Q5/Q6 arrangement is very interesting:

1: Q5 has constant Vce, for better linearity.
2: Vce is high, near 40V, so Cob is very low and bandwidth is increased.

However, I don't think this is necessary. I think you would have the same performance if you just normally cascoded Q5 with a PNP on its emitter and drove the outputs from there.

Also, the MOSFETs each need about 4V of G-D bias to get them in their linear region and into class A.

If you're interested in adding 2 more BJT's you could do a Allison-type output stage with MOSFETs, which would perform very well and would bias itself with little hassle (that is if your output is supposed to be class A). I can help if you're interested.

- keantoken
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Old 28th December 2009, 05:42 PM   #17
sigpl is offline sigpl  Europe
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keantoken, you caught my interest, what is an Allison-type output stage ?
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Old 29th December 2009, 04:11 AM   #18
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Quote:
Originally Posted by sigpl View Post
keantoken, you caught my interest, what is an Allison-type output stage ?
I made a thread about it here:

Simulation Analysis of several unique Allison-based output stages.

The possibilities of the Allison are endless, so to keep from being incredibly vague I've attached what I had envisioned. The whole idea revolves around Q8 and Q7, which I call the Allison transistors. It is important that their emitters are joined and that they must share the same current.

I also might suggest the JLH output stage. It would integrate nicely with the circuit. Look at Tr1, 2 and 3 in figure 3.

http://www.tcaas.btinternet.co.uk/jlh1969.pdf

- keantoken
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File Type: png AllisonMosfet+LTP_VASCascode_g20.PNG (21.0 KB, 40 views)

Last edited by keantoken; 29th December 2009 at 04:13 AM.
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Old 29th December 2009, 08:34 AM   #19
godfrey is online now godfrey  South Africa
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Hi keantoken
In your Allison thread, the image in the first post won't expand , so it's hard to see what's going on.
If you have the image saved someplace, it would be great if you could repost it (here or there). Maybe one of the mods would be kind enough to replace the original pic in the Allison thread?
Cheers - Godfrey
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Old 29th December 2009, 08:52 AM   #20
godfrey is online now godfrey  South Africa
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Quote:
Originally Posted by sigpl View Post
... step response of the current thru Q6 (with resistor R4 this corresponds to a near 20 V step in 20ns). Unfortunately the step is not that good after the FETs, but that is due to them solely (or?).
The step response of the voltage on the collector of Q6 will be much slower than the current step through it. Mosfets have very high DC input impedance, but also a fair amount of input capacitance, so the current through Q6 has to charge and discharge this capacitance as well as driving R4. The voltage step at the output should be almost as fast as the voltage step at the collector of Q6.
Quote:
Originally Posted by sigpl View Post
... the MOSFETs draw a lot of current on the gate (up to 0.5mA), not DC but when applying the signal source. How come?
Same story. The higher the frequency, the higher the current needed to drive the gate capacitance.
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