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Old 26th December 2009, 03:04 PM   #121
BV is offline BV  Slovakia
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Fuse in ouptut can save nothing (it is too slow), only decreasing DF and increasing THD at low frequencies (thermal modulation of fuse resistance).
Now it is time to makae some antisaturatin modifications for fast recovery (try to inspect limitation at 120kHZ and look for "rail "sticking" !) and overcurent protection.
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Old 26th December 2009, 03:11 PM   #122
GK is offline GK  Australia
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The 33R bypassed by 22nF on driver bases are calling for trouble, you usually want resistive input impedance at high frequencies and low impedance at low frequencies (R and L in parallel).

No, you generally want just plain resistors - any inductance in in series with the transistor input capacitance is just asking for trouble.


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The 100uF in parallel with the Vbe multiplier is calling for local instability, a capacitor should not be placed there without series resistance, the output impedance of a Vbe multiplier is actually quite low due to the high local feedback.

As a matter of fact the 100uF capacitor actually provides a dominant pole frequency (shunt) compensation of the Vbe multiplier at a very low frequency, positively eliminating any chance of local oscillation. And a single transistor Vbe multiplier does not have a particularly high amount of local negative feedback or a very low dynamic impedance.


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You may find that diodes work better than the 100R and 200R on the rails..

No, you won't. The resistors in conjunction with the large value electrolytic bypass caps are mandatory for low-pass filtering the HF junk on the power rails from the input stage and VAS circuitry due to the diminishing HF PSR. You can look up a complete discussion of this in the handbook.


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2.2uF between the emitters of the drivers is also calling for local instability. Sometimes things don't work as expected (when you are only interested in the simple answers to complex questions)...

Yawn. With a basic double EF you will only get a local instability here with that 2.2uF cap in place if the layout is particularly bad or if you do something silly such as leaving out some adequately sized base stopper resistors for the driver transistors.
The 2.2uF is actually there to speed up switching of the power output transistors. Again, you can look up a complete discussion on this in the handbook (one of the distortion mechanisms).


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The 100R to 2.2R ratio of the BC546/BD139 emitter resistors is also calling for trouble (45). Emitter degeneration is used to force a lower current gain and get low phase shift up to a higher frequency in return. Theoretically a 100Mhz Ft transistor with a forced gain of 50 will roll off at 2Mhz, this is too low. Forced gains are usually 10 or less to get higher bandwidth.

This makes no sense whatsoever. While the 2.2 ohms is rather pointless, the ratio of the resistances is irrelevant. The VAS is actually operating as an intergrator due to the local negative feedback provided by Cdom and any influence of that 2.2 ohms on the "bandwidth" of the VAS is non existant.
The 2.2 ohms would be better removed* as it does nothing usefull and the 100R biasing resistor for the VAS buffer emitter follower should be increased to 1k - there is no linearity benefit to be had running the EF for the VAS so hot.

*although some form of clipping current limiting needs to be implemented for the VAS EF - I'd fix its collector voltage to 10V above the negative rail with a zener biased with a resistor to ground.

Last edited by GK; 26th December 2009 at 03:41 PM.
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Old 26th December 2009, 03:34 PM   #123
wahab is offline wahab  Algeria
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Originally Posted by GK View Post
As a matter of fact the 100uF capacitor actually provides a dominant pole frequency (shunt) compensation of the Vbe multiplier at a very low frequency, positively eliminating any chance of local oscillation. And a single transistor Vbe multiplier does not have a particularly high amount of local negative feedback or a very low dynamic impedance.

not always...and i simulated this amp..


.
The 2.2 ohms would be better removed as it does nothing usefull and the 100R biasing resistor for the VAS buffer emitter follower should be increased to 1k - there is no linearity benefit to be had running the EF for the VAS so hot.

actually, 100R is too low and 1K is too high...
also using this schematic simulations..



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Old 26th December 2009, 03:44 PM   #124
GK is offline GK  Australia
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not always...and i simulated this amp..

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actually, 100R is too low and 1K is too high...
also using this schematic simulations....

Oh, great, proved by the simulator..........
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Old 26th December 2009, 03:45 PM   #125
wahab is offline wahab  Algeria
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Oh, great, proved by the simulator..........

still one step further than visual evaluation...no?..
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Old 26th December 2009, 03:52 PM   #126
GK is offline GK  Australia
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still one step further than visual evaluation...no?..

At this stage, hardly.
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Old 26th December 2009, 03:55 PM   #127
wahab is offline wahab  Algeria
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anyway, even visually, the vas buffer should see a higher current
than a tail of the differential, but not as much as the vas..

1K make it lower than the differentials currents..
it deacrease dc offset cancellation efficency by the way..
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Old 26th December 2009, 04:03 PM   #128
GK is offline GK  Australia
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anyway, even visually, the vas buffer should see a higher current than a tail of the differential,

Why? Do you have a valid technical reason here, or can we just say it's so?
From (vague) memory (in the section of the handbook discussing the (zip) merit of alternatively loading the EF with a current source) it was stated the there was no measurabe benefit from using a resistor here any lower than 1.5k or so.

With a modern, high fT, low Cob transistor for the VAS it would be even less of an issue.
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Old 26th December 2009, 04:03 PM   #129
Eva is offline Eva  Spain
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Quote:
Originally Posted by GK View Post
No, you generally want just plain resistors - any inductance in in series with the transistor input capacitance is just asking for trouble.





As a matter of fact the 100uF capacitor actually provides a dominant pole frequency (shunt) compensation of the Vbe multiplier at a very low frequency, positively eliminating any chance of local oscillation. And a single transistor Vbe multiplier does not have a particularly high amount of local negative feedback or a very low dynamic impedance.





No, you won't. The resistors in conjunction with the large value electrolytic bypass caps are mandatory for low-pass filtering the HF junk on the power rails from the input stage and VAS circuitry due to the diminishing HF PSR. You can look up a complete discussion of this in the handbook.





Yawn. With a basic double EF you will only get a local instability here with that 2.2uF cap in place if the layout is particularly bad or if you do something silly such as leaving out some adequately sized base stopper resistors for the driver transistors.
The 2.2uF is actually there to speed up switching of the power output transistors. Again, you can look up a complete discussion on this in the handbook (one of the distortion mechanisms).





This makes no sense whatsoever. While the 2.2 ohms is rather pointless, the ratio of the resistances is irrelevant. The VAS is actually operating as an intergrator due to the local negative feedback provided by Cdom and any influence of that 2.2 ohms on the "bandwidth" of the VAS is non existant.
The 2.2 ohms would be better removed as it does nothing usefull and the 100R biasing resistor for the VAS buffer emitter follower should be increased to 1k - there is no linearity benefit to be had running the EF for the VAS so hot.
Inductance in parallel with resistance and in series with input capacitance won't resonate when tuned properly and will change the reactive input impedance of the bases back into resistive.The purpose of the inductance is to bypass the resistor at low frequencies.

The 100uF capacitor does have some inductance... And there is a second pole from Vbe multiplier transistor roll-off added to the pole from the capacitor. I know local Vbe multiplier instability because it happened to me. A zero was required at the oscillation frequency (by adding some series resistance) for stability.

The diodes do an interesting filtering work because the capacitors in the other side only get charged when short term output power is low and power supply recovers from sag. Then, input stage supply rails get completely disconnected when output power is high and power supply sags again. This allows for lower THD near the rails, and if an oscillation problem due to cross-talk was present, the diodes would prevent sustained oscillation.

Again, the 2.2uF capacitor has some series inductance, and the transistors also exhibit some series inductance. For example, 2.2uF with 40nH resonates at 530Khz... The worst capacitor that can be placed there is a film or ceramic. A small electrolytic is ok due to the higher ESR. This problem is something that I have experienced.

Local feedback has precedence over global feedback. A composite VAS can easily oscillate if proper degeneration is not employed. With a simple miller capacitor phase margin is very small because each transistor is producing nearly 90 deg lag at RF, but proper degeneration improves phase margin.

Theoretically, a transistor with a beta of 100 and Ft of 100Mhz should start to roll off at 1Mhz at -6dB/oct (adding 90 deg. of phase shift). Close a miller feedback loop around two of these and they won't hesitate to oscillate, maybe not always but easily near clipping, and transient response will show ringing. If degeneration is employed to force a gain of 10 in one transistor, it will not roll off until 10Mhz. Then it can be used inside a composite Vas if the outer loop is below 0dB gain at 10Mhz.

And sorry, I'm not quoting books, I'm talking about problems that I experienced in the past (that is, before class AB became boring for me).
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Old 26th December 2009, 04:23 PM   #130
wahab is offline wahab  Algeria
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Why? Do you have a valid technical reason here, or can we just say it's so?
From (vague) memory (in the section of the handbook discussing the merits of loading the EF with a current source) it was stated the there was no measurabe benefit from using a resistor here any lower than 1.5k or so.

With a modern, high fT, low Cob transistor for the VAS it would be even less of an issue.

i was thinking like you...until i simulated around this with
simple circuits about the dc operating points..
the simulator is accurate enough for static measurements..

in the original d. self amp, the following must be made :
vas buffer resistance should be about 270R and the VAS must have
a degeneration resistance of 43R...
output dc offset will then deacrese to normal value for
an op amp topology like this, i.e, from 1.475 mV to +-50 uV...
perhaps it s a device dependency..
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