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Old 2nd December 2009, 05:14 PM   #1
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Default THD distortion HELP!!!

Hi:
Can anyone help me by giving me advise on how to perform an actual 0.006% THD of the circuit Blameless cause I am stuck on the circuit. I found out that my circuit THD is 0.63 and it is still high enough. I hope someone can give me some advise on how to reduce THD?
Is there any other issue caused the circuit THD to be so high?

Below is the diagram of Blamesless circuit and THD Spice Log and FFT graph Diagram.

THD.JPG

FFT.JPG

circuit.JPG
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Old 2nd December 2009, 05:35 PM   #2
wahab is offline wahab  Algeria
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first try is to remove collector of TR12 from ground, and connect it to collector of TR4....
a more radical step is to remove TR12 itself and only use one trans in the vas...
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Old 2nd December 2009, 05:51 PM   #3
wahab is offline wahab  Algeria
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this amp doesn t exactly hold its name...
it work well if you remove TR12 and R30, and then connect the
base of TR4 directly to collector of TR10....
C3 must be kept as it is from collector of TR10 to collector
of TR4...
beside, it will eliminate the strange behaviours we can see
in the spectral analysis...
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Old 2nd December 2009, 05:59 PM   #4
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Try setting the value of the bias pot, PR1, to 211 before you do any other changes. When I run a sim on this circuit using models for the transistors he shows (except outputs, I didn't have those) I get THD of 0.004%.
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Old 2nd December 2009, 06:47 PM   #5
jcx is offline jcx  United States
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actually 1st try is setting up the sim and verifying you can meassure low thd by looking at the input sinewave distortion

look for my (jcx) posts containing "plotwinsize" or "fft" keywords for LtSpice settings for high resolution distoriton measurements
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Old 2nd December 2009, 07:17 PM   #6
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thanks WAHAB for the advise .. i try to cut off the TR12 . but it still the same of THD 0.6 something . I wondering y like this.
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Old 2nd December 2009, 07:26 PM   #7
wahab is offline wahab  Algeria
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it seems that dunlap got it right, it must be crossover distorsion...
try what he says and set the power transistors idle current to 5O mA..
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Old 2nd December 2009, 07:26 PM   #8
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Try setting the value of the bias pot, PR1, to 211 before you do any other changes. When I run a sim on this circuit using models for the transistors he shows (except outputs, I didn't have those) I get THD of 0.004%.

I've try to tune until 211 and this also seem to be the same. do u mean ur models all the same ? I using the
BD 139 npn for the medium power trans Vceo=80V Icrating =1.5
QMJE15030 npn for the power transistor Vceo=150 Icrating=10
QMJE15031 pnp for the power transistor Vceo=150 Icrating=10
QMJL4281A npn for the power transistor Vceo=350 Icrating=15
QMJL4302A pnp for the power transistor Vceo=350 Icrating=15
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Old 2nd December 2009, 07:31 PM   #9
tomchr is offline tomchr  United States
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Check the bias currents by running a DC sim. If everything checks out to reasonable values, then run a transient sim with a sine wave input. If that looks good, then I'd probably run an AC sim of the open-loop gain (AVOL). If AVOL looks decent, then start looking at THD.

It is of course possible that you've already done all of that and now you're stuck on the THD. But I would find it odd if you didn't notice any oddities along the way.

I remember running THD sims on Self's Trimodal amp (blameless with class A/AB switching) back in the mid/late 1990'ies using PSpice and getting THD figures on the order of 0.001 %. Better than I could measure in the lab.

What does the THD look like at 1 kHz? How about 100 Hz?
Are any of the internal stages slewing in your 10 kHz sim?

~Tom
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Old 2nd December 2009, 07:40 PM   #10
rdf is offline rdf  Canada
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Quote:
Originally Posted by jcx View Post
look for my (jcx) posts containing "plotwinsize" or "fft" keywords for LtSpice settings for high resolution distoriton measurements
And 'timestep'. It looks like an LTSpice artifact.
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