Wildcard Power Amp dev. thread (SMD, Quasi NMOS, IRFP260, digital bias)

[danfo098]

I've been thinking about a quasi complementary NMOS amplifier with digitally controlled bias for quite som time now and here is my first preliminary schematic.

I'm a bit curious about what you have to say about D1, D2, D3 and D4. Do you see any problems with them connected like that?

The uC that will do the monitoring will use the -V rail as ground and a separate 5V/3.3V supply. The output bias will be set with V3 (one of the uC DAC:s) and read back by measuring the voltage over R20, R21, R24 and R25. Some op-amps for amplification/attenuation and differential amplification will be needed but are not currently in the schematic.

The quiescent current will be monitored and adjusted continuously for thermal tacking. The method I was thinking to use is simply to measure the voltage over the source resistors in the crossover point (when the voltage over the high side resistors equals the low side resistors) and then calculate the current (with some averaging).

Are there any other smart methods to measure the quiescent current with signal applied? Maybe measure the RMS power in the speaker and the total RMS power and from the difference get the quiescent current?
But this should only work when the signal is a sinusoid or some other known signal? Or am I wrong here?

[tiefbassuebertr]

go to post #40 about
Only N-Channel MOSFETs (NMOS); better Audio from non complements by Audio Power?
and check out the last two URL's

[effebi]

Originally Posted by danfo098

Are there any other smart methods to measure the quiescent current with signal applied? ?

You may use a VERY low pass filter.