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Old 24th September 2009, 09:46 AM   #1
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Default thermal stability of parallel FETs

The stories of thermal runaway of paralled Lovoltech LU1014D power JFET that I heard motivated me to do some thinking on the thermal stability of FETs.

Positive tempco of FETs running at relatively low current, causing current hogging and thermal runaway of some FET, is a common problem when designing an audio amp with parallel FET devices.

I'm thinking of sharing some of my ideas of how to predict the thermal stability of single/paralleled FET devices used in saturation region using the following information:
thermal resistance of Juction to device Case
thermal resistance of isolation pad
thermal resistance of heatsink
curves of Vgs vs Id for different temperature
Vds and Id
Vgs dismatch between a group of FETs at the working Id

Before I start writing, I'll like to know if any one have seen articles discussing similiar topics (thermal stability of FET in saturation region)?
I tried some search but only found discussions of how FET is inherently thermally stable in Linear region.
I will like to absorb some thoughts of other people and avoid reinventing the wheel.

Zhou Fang
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Old 24th September 2009, 09:24 PM   #2
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I was warned off IRFP240/9240 devices as I was told it was hard to stop thermal runaway.

If you use a good bias circuit then there really shouldnt be any problems.
The bias will back off as the transistors get hotter.

I also go for as low bias as possible by adjusting the bias to just get rid of crossover distortion.

I also always add a good size heatsink to my amps with a couple of fans to stop the amp getting hot in the first place.
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Old 25th September 2009, 01:18 PM   #3
ilimzn is offline ilimzn  Croatia
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IRFP devices are enhancement MOSFETs with a positive Id tempco up to close to their maximum Id. They will work just fine provided a proper bias generator with temperature compensation is used - no bigger a deal than with BJTs, in fact, even less of a problem.
The lovoltech devices are power JFETs, which are 'slightly' different in this regard...
Paralleling any high gm device will lead to some form of current hogging, even in negative tempco devices... but this is a different issue altogether.
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Old 25th September 2009, 02:47 PM   #4
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I don't think Zhou Fang's question was about thermal runaway, but rather about current sharing. These are somewhat related but not the same. For instance, current sharing does not depend on what the bias generator looks like, that only matters for thermal runaway where it is heatsink temperature that runs away. Having a good bias generator won't stop current sharing imbalance from occuring.

Thermal stability of a transistor or similar device at a certain operating point can be determined by calculating the amount of positive thermal feedback. The following formula assumes the operating point is at a constant Vds and constant Vgs. If it is total current of parallelled transistors that is fixed instead of Vgs, this still works very well as an approximation as long as current mismatch isn't big enough to cause significant differences in transconductances and temperature coefficents.

Thermal positive feedback is:
k = Gm * Vds * Rth(j-common point) * (-dVgs/dT)

where
Gm = combined transconductance of one output device and its ballast resistor at this operating point
Vds = drain-source voltage at this operating point
Rth = thermal resistance to common temperature, per transistor in K/W.
dVgs/dT = temperature coefficient of Vgs in V/K at constant drain current at this operating point

If k is between zero and one, then the amplification of inital imbalances (such as from unmatched transistors or slightly different thermal resistances) is A = 1/(1-k). (sum of infinite geometric series)

As k goes towards one, the amplification grows toward infinity. When k >= 1 the amplification of any inital mismatch is infinite.

Something that must not be overlooked is that ensuring sharing stability at the bias current may not be enough to ensure it at higher current if transconductance rises toward higher current. However, this is somewhat counteracted in class AB amplifiers by the thermal time constants of the transistors and the duty cycle.

Also, be careful if devices are not close to each other on the heatsink. In that case, using Rth(junction-sink) as the Rth(j-common point) is too optimistic. To let Rth(j-common point) = Rth(j-s) + Rth(shared sink - ambient) * (number of transistors) is an alternative, but it's bound to be overconservative.

Last edited by megajocke; 25th September 2009 at 02:56 PM.
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Old 25th September 2009, 03:42 PM   #5
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Quote:
Originally Posted by megajocke View Post
k = Gm * Vds * Rth(j-common point) * (-dVgs/dT)
I must thank you for all you have wrote! The information in your post is almost identical to a large portion of what I plan to write. It is assuring to know that my independent calculation is not too far off the mark.


Quote:
Originally Posted by megajocke View Post
Something that must not be overlooked is that ensuring sharing stability at the bias current may not be enough to ensure it at higher current if transconductance rises toward higher current.
For instantaneous higher current due to AC signal, I think the higher gm will also be balance off by instantaneous lower Vds (since high current happens at lower Vds).
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Old 25th September 2009, 03:48 PM   #6
AndrewT is offline AndrewT  Scotland
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Quote:
Originally Posted by zhoufang View Post
how to predict the thermal stability of single/paralleled FET devices .......................I'll like to know if any one have seen articles discussing similiar topics (thermal stability of FET in ....)?
Bob Cordell posted his reasoning and his formula for this topic (both FETs and BJTs) in his interview series of this Forum.

Go and search.
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Old 26th September 2009, 01:29 AM   #7
eyoung is offline eyoung  United States
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I must preface this as a compliment...

Thanks again for being the voice of reason...

Regards, Elwood
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