Bipolar/MOSFET CFP output stage

[ashok]

Has anyone tried using a low power MOSFET transistor with a Bipolar power transistor in a CFP stage. Any comments about its bias stability and the performance?
I wanted to use a Hitachi TO220 package MOSFET with a Bipolar output device like a 2SC3281/2SA1302 ( or similar ) . The idea being that I get a simple high input impedance stage with plenty of current drive capability in the output devices.
Biasing will be like the usual transistor Vbe multiplier.
Essentially like the circuit at:
http://sound.westhost.com/project3a.htm

Q5 and Q6 will be MOSFET's.
Any suggestions?
Thanks,
Ashok.

[hifiZen]

The difficulty here would be the high capacitance of the mosfet, which is loading the VAS. I think the more resistive loading presented by a BJT would be preferable here...

I suspect you may be able to raise the input impedance of the output stage by doing the opposite of what you plan... that is, use a BJT to drive the gate of a mosfet power transistor. Mosfets can easily handle the current, although you will sacrifice some efficiency since you won't be able to swing as close to the rails... But I believe this approach would probably yield an improved input impedance, allowing more linear operation of the VAS.

Thoughts on the above, anyone? I haven't run the numbers on this one yet, but it's in my list of considerations for a new amplifier. The other issue, of course, will be stability... CFP isn't known for being the most stable beast. In this respect, perhaps someone with a bit more experience building mixed bjt/mosfet CFP stages can comment? For what it's worth, I've built a couple of fairly low powered mixed bjt/mosfet CFPs before, and did encounter some oscillation, but YMMV.

[Circlotron]

Originally posted by hifiZen
Mosfets can easily handle the current, although you will sacrifice some efficiency since you won't be able to swing as close to the rails. The other issue, of course, will be stability... CFP isn't known for being the most stable beast.

I minimised the problem of not being able to swing to the rails by soldering one of those little 3 volt coin-shaped batteries like on your pc motherboard, in line with the fet gate. Positive toward gate. This meant the gate threshold was effectively lowered by 3 volts so that means the drain can swing down 3 more volts before the cct runs out of puff.
For stability, try putting a bit of resistance in the emitter of the bjt to lower it's gain a bit. Worked for me at least.

[ted]

It's not a CFP output, but if I remember right a Yorkville AP-1212 used for output, mj15022/23 driven by MOSFET driver(s) (MTW10N40 / MTW14P20). The VAS drive to the MOSFET's was not that more complicate then a standard amplifier.

It's been I while since I played with the Yorkville, so I could be mistaken.

[andy_c]

Hi ashok,

Have you tried using SPICE to model the output stages you're considering? I've been using the freeware LTSpice from Linear Technology to evaluate power amp output stages, and I must say the results have shed a lot of light on the problems. Models for the On Semiconductor equivalent of the 3281 and 1302 are available. If you use International Rectifier MOSFETs, I can provide you with some models that aren't generally available on the net. I don't think I have any Hitachi models though.

For evaluating stability, I pick a worst-case capacitive load. In my case, I used 2uF, a value that Bascom H. King has used for many years as a torture test for amps. As a result of all this, I ended up abandoning bipolar output stages altogether, as the output impedance is quite inductive at high frequencies. This causes a high-Q resonance with the capacitive load, which has horrible effects on the stability of the amp.

Another poster mentioned high capacitance of the MOSFETs. The IRF 610 and IRF 9610 have a typica gate-to-drain capacitance of 15 pF at 25 Vdc. I was pleasantly surprised by how low this is. The gate-to-source capacitance is high, but the Miller effect at a gain of 1 mostly cancels this out.

[Dr G Scott]

You guys are as confused as barking duck.......

The McCormick amps use Hatachi 2SJ76 and 2SK213. The gate to source turn on is low enough that you lose little voltage swing. The VAS boot strap circuit like in http://sound.westhost.com/project3a.htm
would take care of this on the negative swings and it wouldn't take a nuclear physicist to design a circuit for the positive swings, batteries...... please! I would rather have the VAS stage clip than the output when you run out of voltage swing.

All amps (FET BJT Tube) with loop negative feedback have inductive output Z. I won't state the obvious reason why. Put a snubber on it like the real designers do.

A BJT will have the VAS stage see the load impedance divided by Hfe of the output stage. Most speaker loads are not very resistive, especially at cross over frequencies. The guy asking the question knows more than the people offering advice as is often the case.

[andy_c]

All amps (FET BJT Tube) with loop negative feedback have inductive output Z. I won't state the obvious reason why.

Actually, I was referring to the open-loop output impedance, not closed loop. No feedback, just an output stage all by itself. A simple complementary emitter follower circuit with the MJL3281a and MJL1302a biased in class AB at 40-45 mA shows 60 degrees of phase lead in its output impedance at less than 300 kHz. By contrast, the IRFP240/IRFP9240 pair has an almost purely resistive output impedance out to about 1 MHz. With tha bipolar output stage and a 2 uF load, simulations show about 9 dB of peaking in the small-signal open-loop gain (again, of just the buffer), with a very sharp dropoff of phase. With the MOSFETs, the result looks much more like a single-pole rolloff.

[Pjotr]

Hi,

I am thinking to build a class-A amp that way. The main reason is that the FET diver transistors have a quadratic transfer function (in the ideal case). That means the bias current trough the output can be 1/4 of peak output current needed in stead of the usual 1/2 peak output current to keep the amp fully in class-A. The sum of quadrates (of bottom and top fet) will give a linear transfer function.

And for those concerned about capacitive loading of the VAS: The input cap of a source follower is:

C_in = C_gd + C_gs x (1-voltage gain)

Since voltage gain is near unity the effective capacitance of C_gs is very small at the VAS.

[Fred Dieckmann]

The phase angle depends on the source impedance seen by the output. With each base seeing about 10 ohms with respect to ground you should see 60 degrees at over 3 MHz.

X1 3 5 1 QSC3281 { }
.SUBCKT QSC3281 1 2 3
* TERMINALS: C B E
* 200 Volt 15 Amp SiNPN Power Transistor 12-03-1991
Q1 1 2 3 QPWR .67
Q2 1 4 3 QPWR .33
RBS 2 4 9.5
.MODEL QPWR NPN (IS=1.63P NF=1 BF=150 VAF=254 IKF=12 ISE=1.34N NE=2
+ BR=4 NR=1 VAR=20 IKR=16.5 RE=22.1M RB=4 RBM=.4 IRB=5.556U RC=4.84M
+ CJE=481P VJE=.6 MJE=.3 CJC=312P VJC=.22 MJC=.2 TF=5.33N TR=204N)
+ XTB=1.5 PTF=120 XTF=1 ITF=9.6)
.ENDS
X2 6 8 2 QSA1302 { }
.SUBCKT QSA1302 1 2 3
* TERMINALS: C B E
* 200 Volt 15 Amp SiPNP Power Transistor 12-03-1991
Q1 1 2 3 QPWR .67
Q2 1 4 3 QPWR .33
RBS 2 4 9.5
.MODEL QPWR PNP (IS=1.63P NF=1 BF=130 VAF=254 IKF=11 ISE=1.34N NE=2
+ BR=4 NR=1 VAR=20 IKR=16.5 RE=12.1M RB=4 RBM=.4 IRB=5.556U RC=4.84M
+ CJE=1.09N VJE=.6 MJE=.3 CJC=708P VJC=.22 MJC=.2 TF=5.33N TR=204N)
+ XTB=1.5 PTF=120 XTF=1 ITF=9.6)
.ENDS
R1 4 2 0.22
R2 1 4 0.22
V1 3 0 DC=50
R3 3 5 775
R4 5 0 10
V2 0 6 DC=50
V3 7 0 DC=0 AC=100
R5 4 7 100
R6 0 8 10
R7 8 6 775
.END

[andy_c]

Fred,

Thanks for posting that. I'm baffled about the difference. Here's the netlist that LTSpice is putting out. I also have 10 Ohm base resistors, and 0.33 Ohm emitter resistors, with a supply of +/- 56V.

I'm still seeing 60 degrees at 300 kHz. I'm trying to attach the image, but it looks like it needs to be a URL?

Andy

============================
* F:\Program Files\LTC\SwCADIII\My Circuits\PA_output.asc
Q1 N008 N007 N006 0 Qmjl3281a
Q2 N009 N004 N005 0 Qmjl1302a
R1 N006 out 0.33
R2 out N005 0.33
R3 N007 N002 {Rbase}
R4 N004 N003 {Rbase}
V1 N002 N001 {Vbias}
V2 N001 N003 {Vbias}
V4 N008 0 56
V5 0 N009 56
V6 N001 0 {Voffset}
I1 out 0 0 AC 1
.model NPN NPN
.model PNP PNP
.lib F:\Program Files\LTC\SwCADIII\lib\cmp\standard.bjt
.param Vbias=0.56
.param Voffset = -0.0356
;op
.ac dec 100 1000 100e6
.param Rbase=10
.backanno
.end
============================
Models from standard.bjt:

.MODEL Qmjl1302a pnp( IS=5.35257e-14 BF=10000 NF=0.85 VAF=29.806 IKF=1 ISE=6.75503e-13 NE=1.13462 BR=0.1 NR=0.75 VAR=298.06 IKR=10 ISC=1e-16 NC=3.31217 RB=1.9617 IRB=0.1 RBM=1.9617 RE=0.0001 RC=0.185509 XTB=0.1 XTI=1 EG=1.05 CJE=1e-07 VJE=0.4 MJE=0.491105 TF=6.44974e-10 XTF=1000 VTF=2.05556 ITF=279.371 CJC=5e-10 VJC=0.400004 MJC=0.23 XCJC=1 FC=0.1 CJS=0 VJS=0.75 MJS=0.5 TR=1e-07 PTF=0 KF=0 AF=1 Vceo=200 Icrating=15 mfg=OnSemiconductor)

.MODEL Qmjl3281a npn( IS=6.5498e-11 BF=139.247 NF=1.00176 VAF=46.776 IKF=10 ISE=7.75232e-12 NE=3.34341 BR=4.98985 NR=1.09511 VAR=4.32026 IKR=4.37516 ISC=3.25e-13 NC=3.96875 RB=11.988 IRB=0.111742 RBM=0.102914 RE=0.00127227 RC=0.209833 XTB=0.115253 XTI=1.03146 EG=1.11986 CJE=1e-07 VJE=0.4 MJE=0.450375 TF=7.04629e-10 XTF=1000 VTF=2.06045 ITF=41.8156 CJC=5e-10 VJC=0.4 MJC=0.85 XCJC=0.959922 FC=0.1 CJS=0 VJS=0.75 MJS=0.5 TR=1e-07 PTF=0 KF=0 AF=1 Vceo=200 Icrating=15 mfg=OnSemiconductor)