I was putting together a diamond buffer the other day, and I wondered what would happen if the bias current was variable.
One possible way of accomplishing this involves adding only a single component to the common biasing arrangement of JFET CCS + current mirrors, as you can see in the attached schematic. With the second, complementary JFET, the current source can be reconnected as a source-follower in parallel with the diamond buffer. The bias current is now a function of the difference between input and output voltages.
One possible way of accomplishing this involves adding only a single component to the common biasing arrangement of JFET CCS + current mirrors, as you can see in the attached schematic. With the second, complementary JFET, the current source can be reconnected as a source-follower in parallel with the diamond buffer. The bias current is now a function of the difference between input and output voltages.
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And this is what effect it has. The FFT on the left in the attached image is from the buffer with a standard single JFET CCS. The one on the right is with the source-follower variable bias. Measurements were taken at 1kHz, 1Vrms into a 1K load.
In the test circuit, the buffer transistors were BC546B/BC556B, the current mirrors were BCV61C/BCV62C, and the JFETs were 2SK170GR/2SJ74GR.
In the test circuit, the buffer transistors were BC546B/BC556B, the current mirrors were BCV61C/BCV62C, and the JFETs were 2SK170GR/2SJ74GR.
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If the load is light then the current hardly changes at all, and in fact the distortion is worse than the normal CCS version with light loads. As the load is reduced, the current varies more, resulting in the improved distortion shown. Perhaps this means it will make a good output stage for a headphone amp.jam said:
Changing the source-follower for something with higher transconductance (another diamond buffer perhaps) should increase the effect, but the component count would go up a lot.
Are you saying that when the output current is near zero the bias for the diamond pair falls to near zero?
Or does enough bias current flow through the output pair to ensure that there is a bias to the input pair?
What if a small CCS were added in parallel to provide a minimum bias to the input pair and then as output current increases the input pair get more bias to play with.
Or does enough bias current flow through the output pair to ensure that there is a bias to the input pair?
What if a small CCS were added in parallel to provide a minimum bias to the input pair and then as output current increases the input pair get more bias to play with.
Hilee interessent... But could it be made to work with a bootstrap?
Just how close to those 15V rails were you able to go without???
Just how close to those 15V rails were you able to go without???
The quiescent bias current is much the same as in the common CCS biased version, being approximately Idss of the JFETs, minus a bit due to the voltage across R3/R4. The change in bias current is the difference between input and output voltages, multiplied by the source-follower's transconductance. So this change in current is largest when the error voltage is largest, which is when the output current is high.AndrewT said:
I'm not sure how you could work a bootstrap in there, but I don't use them very often so I'm not very familiar with ways to use them.kenpeter said:
Output swing is not a problem; it will go to within approximately 0.5V of either rail with no load, and about 1V with a 1K load, the same as a normal diamond buffer. However, it won't like the input to be driven to the rails, because the JFET's gate-source junction will become forward-biased, resulting in very low input impedance.
A couple of years ago I bought some PBSS4140DPN complementary dual transistors, i.e. one NPN and one PNP transistor in a package, with the intention of using them in a diamond buffer, but I never got around to using them. They aren't very impressive as individual devices, but they should give ideal thermal tracking.
Here's an FFT using these transistors in a circuit identical to the one in the first post, and under the same conditions. THD is a bit lower at about 0.00075%, but 3rd harmonic is higher (ignore both the higher peaks, they are just noise).
Here's an FFT using these transistors in a circuit identical to the one in the first post, and under the same conditions. THD is a bit lower at about 0.00075%, but 3rd harmonic is higher (ignore both the higher peaks, they are just noise).
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I'm going to have to get used to being able to post multiple images at once...
Anyway, this is the finished circuit. I picked up a laser printer cheap recently, and this is the first PCB I made using the toner-transfer method. It worked a treat - double sided too.
The observant among you may notice that all the resistors are 2R2. I initially tried using such a small value for degenerating the current mirrors, but it proved too small even with the monolithic mirrors. It worked fine at low voltages, but at higher supply voltages the Early effect caused the current to increase rather a lot. If the mirrors were cascoded it would have been ok.
EDIT: I completely forgot to mention - I used 2SK209/2SJ106 JFETs for this, since they are the only suitable SMT JFETs I have. They are not complementary at all, which probably accounts for the increase in 3rd harmonic distortion. I don't suppose anyone knows of any decent complementary SMT JFETs?
Anyway, this is the finished circuit. I picked up a laser printer cheap recently, and this is the first PCB I made using the toner-transfer method. It worked a treat - double sided too.
The observant among you may notice that all the resistors are 2R2. I initially tried using such a small value for degenerating the current mirrors, but it proved too small even with the monolithic mirrors. It worked fine at low voltages, but at higher supply voltages the Early effect caused the current to increase rather a lot. If the mirrors were cascoded it would have been ok.
EDIT: I completely forgot to mention - I used 2SK209/2SJ106 JFETs for this, since they are the only suitable SMT JFETs I have. They are not complementary at all, which probably accounts for the increase in 3rd harmonic distortion. I don't suppose anyone knows of any decent complementary SMT JFETs?
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Because the diamond buffer has finite transconductance, there is a voltage difference between input and output. In this circuit, that voltage is the gate-source voltage of the FETs, and since they control the bias current, the bias varies with output current.
I do actually have a few of those, but they all happen to have very different Idss. I'll have to get some more and see if I can get some closer pairs since the ranges overlap.
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