I have a question regarding the design of differential input stages - the schematic I'm looking at is here from the "solid state wiki":
http://sound.westhost.com/project3a.htm
The question I have from the diagram is that if I'm understanding the circuit correctly, the base of Q4 is sitting about a diode drop below Vcc or 35 volts. Now when the input to amplifier is positive going, the output is negative going and the voltage at the base of Q4 turns on the transistor more, causing the output at Q4's collector to rise.
However, when the input to the amplifier is negative going, it looks to me like the voltage at the base of Q4 will rise from Vcc minus a diode drop and cut off the transistor! So how does this input stage (which seems a fairly common circuit) generate the "other half" of the output?
http://sound.westhost.com/project3a.htm
The question I have from the diagram is that if I'm understanding the circuit correctly, the base of Q4 is sitting about a diode drop below Vcc or 35 volts. Now when the input to amplifier is positive going, the output is negative going and the voltage at the base of Q4 turns on the transistor more, causing the output at Q4's collector to rise.
However, when the input to the amplifier is negative going, it looks to me like the voltage at the base of Q4 will rise from Vcc minus a diode drop and cut off the transistor! So how does this input stage (which seems a fairly common circuit) generate the "other half" of the output?
It doesn't matter what "polarity" the input voltage is, because the closed loop circuit causes the voltage at the base of Q2 to be whatever it needs to be to maintain the output at the correct level. In other words, Q1 and Q4 will still conduct as needed to achieve the correct output voltage.
I think I see now. There's feedback at DC into the inverting input of the differential pair Q2, so that DC voltage is coupled into the input transistor through the common connection. So when the input voltage rises from the source signal the output voltage rise is applied as a "bias" voltage to Q1, and the bias voltage follows the input voltage along keeping the transistors in conduction. I think I have that part down now. 
What ensures that the output stays biased at 0 volts though, and not some other value? If there's a good reference online that someone can throw me that describes the operation of this topology in detail, I'd very much appreciate it.
What ensures that the output stays biased at 0 volts though, and not some other value? If there's a good reference online that someone can throw me that describes the operation of this topology in detail, I'd very much appreciate it. 
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