General power amplifier stability discussion (using Spice) - diyAudio
 General power amplifier stability discussion (using Spice)
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 28th April 2009, 08:47 PM #1 diyAudio Member   Join Date: Oct 2008 Location: Vancouver General power amplifier stability discussion (using Spice) I have spent some time searching this site for a good way to judge the stability of a power amp using LTspice, and there seems to be various techniques which seem to give different results. I think this is a popular question but usually atached to a specific circut, so I thought a new thread that was more general made sense. I have seen people also use squarewave response or the slope of the open loop gain, but most use Bode plots, but they use different criteria for these plots: phase margins of closed loop gain, open loop gain, and loopgain (and the confusion starts with these names). In the Spice thread, J. Curl has posted the most comprehensive instructions and a big thanks should go out to him, but there is still confusion. This is the way I understand it. Please correct me if I am wrong! First: most amps are stabilized using a Miller cap (or other integrater) in the cct.. This decreases the high Freq gain, which increases stability, but also increases the HF THD (less feedback). From this I deduce that one should use the the smallest Miller cap possible while maintaining stability. Heres what I have seen: Squarewave response: If there is excesive ringing the amp is unstable, but what does excesive mean. If the slope of the open loop response is to steep its unstable(this one dosnt make sense to me, its not how fast the gain hits zero but what the phase is doing, i know the two are directly related but to use this blanket statement with out showing the bode plot (phase) seems a stretch. The 3 bode plot techniques are the same, phase margin at unity gain, but people use different plots. The only one that works properly is the loopgain plot. (this one takes the fedback into account). This uses the Middlebrook probe method JC has discribed in the Spice thread starting on post 864. I have simmed these different Bode plots of a Blameless amp and got very different phase margins, has any one else tried this? I am I doing somethig wrong?
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Join Date: Aug 2005
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Re: General power amplifier stability discussion (using Spice)

Quote:
 Originally posted by cbdb In the Spice thread, J. Curl has posted the most comprehensive instructions and a big thanks should go out to him, but there is still confusion. This uses the Middlebrook probe method JC has discribed in the Spice thread starting on post 864.

That would be Andy, our LTspice resident expert. JC needs no stinkin' spice, everything was already done 40 years ago, anyway.

Your are essentially correct in your descriptions; the correct stability analysis method is the loop gain phase margin at unity gain.

Post a schematic of your attempt to determine the loop gain phase margin and somebody will guide you through the LTspice specific process.

 28th April 2009, 10:47 PM #3 diyAudio Member     Join Date: Apr 2008 Location: Carlisle, England I think a lot depends on how good spice is. I tend to be old school and wont touch spice. I design a rough circuit then test it and improve it and fix any problems. __________________ Murton-Pike Systems PCBCAD51 pcb design software. http://www.murtonpikesystems.co.uk
 28th April 2009, 10:58 PM #4 diyAudio Member     Join Date: Aug 2007 Location: Niš Try playing with LoopGain.asc and LoopGain2.asc in Educational folder of your LTSpice installation. Also, have a look at this thread http://www.diyaudio.com/forums/showt...53#post1814253 and read about last 10 pages. There are two guys (if I remember correctly) asking questions about calculating open loop gain and phase. Andy C described it very well there. __________________ Windows-free with Linux
 28th April 2009, 11:08 PM #5 diyAudio Member   Join Date: Aug 2004 Location: Behind you My experience is that stability is one of the things that Spice predicts poorly. Amps that are unstable in simulation often turn out to be perfect in reality, and vice versa. This seems to be partly due to poor models, and partly the effect of stray reactance. You can add the latter to the sim, but the former is more difficult to fix. __________________ https://mrevil.asvachin.eu/
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Join Date: Nov 2008
Location: Brazil
Re: General power amplifier stability discussion (using Spice)

Hi

Quote:
 Originally posted by cbdb This is the way I understand it. Please correct me if I am wrong! First: most amps are stabilized using a Miller cap (or other integrater) in the cct.. This decreases the high Freq gain, which increases stability, but also increases the HF THD (less feedback). From this I deduce that one should use the the smallest Miller cap possible while maintaining stability.
Yes is correct, but low values requires quick transitor(low internal capacitance, Cu), may have problems with trasistores similar

Quote:
 Originally posted by cbdb Heres what I have seen: Squarewave response: If there is excesive ringing the amp is unstable, but what does excesive mean. .
Squarewave is another test, for example: may indicate local oscillation in output stage, that is not related the bode plot.
http://users.tpg.com.au/users/ldbutler/Waveforms.htm

Quote:
 Originally posted by cbdb The 3 bode plot techniques are the same, phase margin at unity gain, but people use different plots. The only one that works properly is the loopgain plot. (this one takes the fedback into account). This uses the Middlebrook probe method JC has discribed in the Spice thread starting on post 864. .
No, Middlebrook is more precise for this reason is used.
there 3 bode plot:
1- Open loop gain: You can get bode plot the loop gain (Gain 0/1). Disconnecting the link feedback and connect the base of trasistor Q2 in GND (input - the differential pair )
You can get phase margin in open loop, we assume its open loop is 60dB and its closed loop gain 23dB, just go bode plot and see phase in 23dB we assume 100 degrees,(180-100), its phase margin is 80 degrees, more is not precise measure by this method.
2- Middlebrook: is the difference between open loop and closed -loop, you get the phase margin in 0dB (where it ends the difference between open loop and closed -loop), look the two bode plots you will understand.
3-Closed loop: to gain feedback on

Quote:
 Originally posted by cbdb I have simmed these different Bode plots of a Blameless amp and got very different phase margins, has any one else tried this? I am I doing somethig wrong?
you should remove the input capacitors and zobel output, they are not part of the cycle feedback.

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Join Date: Jan 2006
Quote:
 Originally posted by Mr Evil My experience is that stability is one of the things that Spice predicts poorly. Amps that are unstable in simulation often turn out to be perfect in reality, and vice versa. This seems to be partly due to poor models, and partly the effect of stray reactance. You can add the latter to the sim, but the former is more difficult to fix.

SPICE is poor at predicting parasitic oscillation, but when it comes to examining the phase margin and gain of global and nested feedback loops it can be a very accurate and invaluable tool.

 29th April 2009, 02:20 AM #8 diyAudio Member   Join Date: Nov 2008 Location: Brazil The HFE is fixed in spice, depends on the transistor HFE may vary depending on the temperature.(look datasheet the component) more if you predict that temperature transistor will operate in true circuit, bode plot the simulator will be precise.
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Join Date: Oct 2008
Location: Vancouver
Quote:
 That would be Andy, our LTspice resident expert.
My mistake, appoligies and thanks again Andy C. I would like to post some of my LTspice circuits and bode plots but I am not sure how to do this. (If spice was running on my MAC it would already be done). Could someone please show me the easiest way to make jpegs of these?

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Join Date: Oct 2008
Location: Vancouver
Quote:
 The HFE is fixed in spice
This is not correct. Spice adjusts the transistor HFE (Beta) for different collector currents and temperatures. Run a sim with a current source feeding the base of a transistor with a fixed voltage across the C-E. Then sweep the source and step the temp. and plot Ic/Iq you will see HFE curves (one for each temp step) that should look like the data sheets.

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