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Old 16th April 2009, 02:05 AM   #1
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Default 50W, Class A, another one... :)

Hello.

I haven't been on here for some time as I was tending to matters not electronically oriented. But it feels good to be back.

After the long break I came up with this. To me it seems more practical than my others. With my recent obsession over the Allison, I thought I would take a break from trying to improve it and make a circuit using the original idea.

Click the image to open in full size.

It's still only in simulation. Time rolls by, but so far no money to do anything with. But one good thing: I have a broken Harman/Kardon AVR 35 sitting beside me waiting to either be fixed, or to be gutted, possibly for organ transplants with my new design. I think the only thing wrong with it is blown output devices but I need a service manual (anyone have one handy? ).

The VAS is cascoded, something which I noticed does nicely to reduce distortion. The FET CCS is cascoded to reduce PSRR (this was an experiment of mine, I was wondering if I could use fewer parts). All CCS's are cascoded, except in the output stage, as they are all important.

Squarewave is good, but the thing mangles anything above 50KHz, I think because of the Cdom value. C9 and C10 really help stability.

Because of the cascodes, it won't go rail-to-rail output, but I think that's just fine.

THD@40W, 1KHz = .00028%
THD@40W, 20KHz = .00059%

Note that these are simulated values, I cannot predict what will happen if it is built.

Simulation file is attached. If you need models, say so.

Thank you for your time and any comments or suggestions.

- keantoken
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File Type: zip simpleallison_cascoded_good_2.zip (2.6 KB, 183 views)
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Old 16th April 2009, 11:24 AM   #2
AndrewT is online now AndrewT  Scotland
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50W of ClassA from +-24Vdc supplies seems like you are biasing to suit a 4r0 load.
That's 2.5A bias dissipating 120W/ch

What voltage have you got across J2?
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Old 16th April 2009, 09:47 PM   #3
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Do you mean RMS power or something? I still haven't gotten the RMS thing down yet. But the max output is 40V pk-pk. So +20V/8=2.5, 2.5*20=50W. Okay, I'll bet I'm doing this in a very nonstandard way.

Oh well. You probably get what I mean. Bias current is 1.5A. So maximum current is 3A, though to get this much out we would have to use a smaller load because the output swing is limited by the cascodes.

J2 has about 2.4V on it. Is this not optimal? I know nothing about Jfets.

- keantoken
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Old 16th April 2009, 10:00 PM   #4
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Quote:
Originally posted by keantoken
Do you mean RMS power or something? I still haven't gotten the RMS thing down yet.


- keantoken

((20/sqr2)^2)/8 = 25W
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Old 16th April 2009, 10:11 PM   #5
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Oh, duh. Okay.

25W it is!

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Old 17th April 2009, 12:20 AM   #6
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Here is a simple way to add overcurrent protection.

As the Allison transistors turn on or off, there will be about 700mV between the Allison center and the output at maximum current.

Click the image to open in full size.

- keantoken
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Old 17th April 2009, 09:09 AM   #7
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one pair of plastic packaged 180W devices dissipating 72W of quiescent bias is quite high.
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Old 17th April 2009, 09:46 AM   #8
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Keantoken,
At about the same time that you posted your circuit here (midday my time), I was just printing out a similar design for a small Class A Allison bias amplifier. As your output stage was so similar to mine I thought I'd compare them - they weren't the same!

Your output stage has a nasty high frequency response peak around 1 MHz (I think) that would almost certainly cause it the real circuit to oscillate. It took some time to determine why my design didn't have this effect. The final solution was an emitter resistor in the output driver transistors, plus a more conventional Allison frequency compensation scheme - see attached pdf.

Some other minor things:
- LED current was too high,
- Allison bias current could be a bit higher,
- BC54x transistors are not suitabe as drivers, as the power dissipation is too high. Use mje340/350 or BD139/140 or similar.
- I haven't looked at the input stage.

Yesterday I did a large number of LTspice simulations comparing overalll feedback and no overall feedback. Some interesting results:
- Overall feedback reduced THD, by reducing 2nd and 3rd harmonics, but slightly increased the higher orders.
- Looking at the 7th harmonic (the really nasty one), overall feedback actually increased this distortion.

If I build one of these amplifiers, I'll use feedback around the input stage, and no overall feedback. While the THD is worse, the spectrum looks better! I'm currently looking at either an lme49860 input stage or a discrete ad797 clone. The ad797 clone is currently winning.

Paul Bysouth, April 2009
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Old 17th April 2009, 09:50 AM   #9
AndrewT is online now AndrewT  Scotland
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Quote:
Originally posted by PaulBysouth
....... as drivers, ......... Use mje340/350 or BD139/140 or similar.
these are not similar.
Which parameters should be selected for similarity?
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Old 17th April 2009, 11:09 PM   #10
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For the Allison, I put gain linearity most important, because the input current of the drivers determines the input impedance linearity of the Allison. With more linear devices, it will perform better with higher source impedances. The 2SD669/2SB649 are working well right now.

Quote:
one pair of plastic packaged 180W devices dissipating 72W of quiescent bias is quite high.
The simulator says they are dissipating about 18W idle each. Bias current is about 1.3A.

Okay, maybe I should have asked this question earlier, but what exactly constitutes a dangerous response curve?

Quote:
Your output stage has a nasty high frequency response peak around 1 MHz (I think) that would almost certainly cause it the real circuit to oscillate. It took some time to determine why my design didn't have this effect. The final solution was an emitter resistor in the output driver transistors, plus a more conventional Allison frequency compensation scheme - see attached pdf.
The peak in my simulations is around 30MHz and 80MHz when using the 2SD/2SB pair. In my simulations, most of those additions except for the 1k resistors had a negative affect and usually caused oscillation. Are we doing things differently somehow?

Some odd observations:

1: With all driver transistors (BD1xx, MJExxx) except for the 2SD/2SB pair, distortion and response went down the tube upon the addition of R10 and R11 (also noted that the BD1xx devices were the worst to use, while the MJExxx ones did fairly well). Is this possible or is it a model error maybe? Using the 2SD/2SB pair, distortion actually went down.

With the following simulation, I got the following response curve:

Click the image to open in full size.
Click the image to open in full size.

- keantoken
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