Some elementary questions about dumb-simple MC stage design

[Axon]

Hey - I'm considering building an MC phono stage, but I'm a little curious about exactly how far I can scale down the complexity of the design (my design and construction skills are rusty). I'm slowly going through the several tens of thousands of posts on the subject , but I wanted to throw out some general questions to see if I'm going in the right direction here. I believe I've searched for these questions adequately but lemme know if I haven't.

Some background: I think my configuration is different enough from earlier designs to possibly warrant not merely copying an existing design. I'm targetting my AT OC9 with a 12 ohm source resistance and around 100pF cable capacitance. The preamp will be flat (no RIAA). Input and output is balanced XLR. (Yes, this is a mic preamp in all but name.) I'm looking very hard at the AD797 for this application. I am intending this to be a LOMC-only, balanced-only design. I'm most concerned about noise performance than anything else save complexity and price: I'd be happy if I could get the noise figure under 10db, but I'd be tickled if it could get down to the theoretical 5db or so.

• The AD797 appears to be the best option here because of its excellent noise performance at low source impedances. ?
• Most of the AD797-based designs I'm seeing are using discrete input stages with JFETs like 2SK170s. The only clearly defined reason I'm seeing for this, so far, is to handle the higher source impedance of MMs because of the AD797's poor input offset current performance. (In fact the AD797 is advertised as perrforming remarkably well at low source impedances.) If I make this an MC-only design, can I remove the JFETs and use the AD797 for the input stage? Or does the input bias etc generally preclude this?
• Since I'm not using RIAA eq, can I remove the active circuitry usually involved with the output stage? Or is it still needed for buffering (even though the AD797 advertises pretty good capacitive load handling)?
• Putting the preceding two points together: Is it feasible to use just one amp stage for this?
• If no transistors are used, given the excellent PSRR of the AD797, can I reduce power supply complexity - say, down to a good wall wart plus caps?

[SY]

I'm rather rusty on low noise IC design, but let me give it a shot (willing to be corrected by my superiors).

First, balanced is good.

From the en and in specs on the datasheet, optimum source resistance at 1kHz to minimize noise figure is on the order of 500R. So I don't think you'll quite meet the noise figure targets. If you'd consider a 1:2.5 stepup transformer, you'll nail it and take care of balance at the same time. (Not that I know where you'd find such a transformer)

However... let's see if it's Good Enough. The output spec is 0.4mV (no velocity given), so let's use that as a reference voltage. The en will dominate the noise performance. The en curve shows a rise below 100 Hz and flat thereafter. Let's choose a bandwidth of 20kHz. The integrated voltage noise over a 1MHz bandwidth is specified at about 1uV. So ratioing the bandwidths and square rooting, the expected noise from the chip should be about 0.14uV. Referenced to the 400uV cartridge output, that's about -69dB. Not too shabby.

There are some outrageous approximations in here, but still, you can get this pretty quiet if not ultimately so.