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Old 25th January 2009, 06:19 PM   #21
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Quote:
Originally posted by ostripper


That is strange.., AC coupled offset adjust???
Does that use the ESR of the cap to affect the offset?
OS

The cap is parallel with the pot and so will not effect the bias setting. It is there to help prevent oscillations.
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Old 25th January 2009, 06:21 PM   #22
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Quote:
Originally posted by sakis
A)what about output resistors ..... amplifier i worked with (Legend4) didnt include any and all forum members were screaming about this ..... similar to this is the discusion about the JOY 200 amplifier ( an sziklai with 4 out transitors with out any out resistors ) so what's the catch here ????
I believe you are referring to Source Resistors. For mosfet outputs, you can do away with source resistors but all the mosfets need to be tightly matched so that there's no current hogging.

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B) since legend 4 was didnt include ccs in the vas or ltp stages was called a "POOR " design and not really stable as far as i can see from this schematic at least in the ltp stage there is no ccs here also . ......
CCS results in superior PSRR. Some designers prefer to use a resistor instead. I believe their reason is it sounds better.

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C) can somebody tell me if this design is stable ???? then again how much power ???? and what is the rail voltage ...????
There is nothing fundamentally wrong with the design to render the amp unstable unless the compensation caps are of wrong values. Similar in design to my Lm60 (see below) except for power rails at 118V. At such high rail voltages, I would expect about 400W 8 ohms 1 kHz Sine.

What is surprising though is the current in the VAS. Its hard to make out in the schematic but if R12 is 240R, that would mean about 5mA per leg. That's a bit low to direct couple the mosfet current stage. This will result in early Slew Rate Limiting.


Mike
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Old 25th January 2009, 06:22 PM   #23
SQLGuy is offline SQLGuy  United States
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Default Re: ITS NOT !!!!!

Quote:
Originally posted by sakis



you have to look at the schematic again ..... its 12 outs totally but only 4 shown on the schematic ......

What schematic are you guys looking at? The one at the top of this thread clearly shows 12 output devices.
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Old 25th January 2009, 06:28 PM   #24
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Hi SQLGuy

Sakis is referring to the one in Post # 17

Mike
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Old 25th January 2009, 06:41 PM   #25
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Quote:
Originally posted by Steve Dunlap
The cap is parallel with the pot and so will not effect the bias setting. It is there to help prevent oscillations.
Hi Steve
I think you are looking at the wrong pot. Its not RV1 for biasing but RV2 that is supposed to be for DC offset adjustment. I don't see how that can work with C2 there.

Mike
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Old 25th January 2009, 07:22 PM   #26
AndrewT is offline AndrewT  Scotland
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RV1 sets the output bias.
RV2 is a horrible way to set the input offset to cancel output offset.
Could C2 be deliberately selected to be a leaky electrolytic?

Even matched Lfets require some source resistance to balance output current.

Is the 115Vdc on the voltage amp stage really so much higher than the 60.5Vdc on the output stage?

200mA through each Lfet and a total of 1.2A of FET bias. The designer must have been paying attention to Borbely.
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Old 25th January 2009, 07:23 PM   #27
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Quote:
Originally posted by Michael Chua


Hi Steve
I think you are looking at the wrong pot. Its not RV1 for biasing but RV2 that is supposed to be for DC offset adjustment. I don't see how that can work with C2 there.

Mike

You're right. I was looking at the bias pot. VR2 is not for DC offset adjustment. DC offset is handled by C4/C5 and no adjustment should be needed unless one or more of the caps has become leaky (as was mentioned earlier in the thread). VR2 appears to be feedback to improve PSRR.
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Old 25th January 2009, 07:27 PM   #28
AndrewT is offline AndrewT  Scotland
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Ungie,
if you want to bin it, I'll pay the carrier to get it to the UK.

I'll add the followers between the VAS and the output FETs.
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Old 25th January 2009, 07:33 PM   #29
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Quote:
Originally posted by AndrewT
Even matched Lfets require some source resistance to balance output current.
Hi Andrew

If the mosfets are well matched, you can do away with Source Resistors.


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Is the 115Vdc on the voltage amp stage really so much higher than the 60.5Vdc on the output stage?
The output stage is at 118V. Voltage amp at 113V.

Mike
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Old 25th January 2009, 07:55 PM   #30
AndrewT is offline AndrewT  Scotland
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If I'm able to read it correctly the schematic in post1 shows +60.5Vdc and a voltage doubler off the AC to generate 113Vdc for the low current stage (voltage amp).
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