PSRR, topologies, device characteristics

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Sy originally said:

>>>A cheezy opamp like an LF351 will have a PSRR of about 50 dB at 10KHz, and dramatically better performance at lower frequencies where the ear is more sensitive. A decent opamp like the AD797 (designed by one of my drinking buddies) will show something more like 80 dB at 10KHz.<<<

>>>Of course, the frequencies at which PSRR tails off are exactly those where proper bypassing can take care of things quite well.<<<

To which I responded:

>>SY: Do you reckon that the bootstrapping of the second-stage summing current mirror is partly responsible for the better-than-normal PSRR of the AD797? When I tried this, I remember that it certainly added loads of open-loop gain, but I don't seem to recall how it affected the PSRR.<<

Sy then answered:

>I don't know off the top of my head. I'll take a look at the schematic. If necessary, I'll ask the designer to put down his glass for a moment and explain it to me.<

Thank you, Sy. The 797 has a couple of interesting twists compared to a normal folded-cascode implementation, and it would be educational to hear the designer's rationale for his choices.

It would be particularly interesting to know whether the 797's PSRR is primarily down the topology, or whether something more is provided by the device characteristics. In my designs, I have found that the Early voltages of the summing current-mirror devices have a notable effect on the negative-rail PSRR, but so far it has been difficult to capitalize on this information - the vast majority of medium-voltage BJTs with low noise and low capacitance have rather high Early voltages, while Early-voltage cancelling topologies are tricky.

For instance, Barry Hilton discusses an Early-voltage cancelling scheme on pages 194~5 of Jim William's compilation "Analog Circuit Design". Has anyone tried this type of topology, or managed to get it working to satisfaction?

best, jonathan carr
 
The Williams approach is frighteningly complex, I have prototyped and simulated this "Super Pair" cirucit but never tested it thoroughly for a product application

Baxendall, “Constant-current source with unusually high internal resistance ..." Electronics Letters , vol 2, 1966, p351
( I haven't read this article but it was referenced in: "Active Filters for Integrated Circuits" W.E.Heinlein and W. H. Holmes, 1974 )


Hawksford, “Reduction of Transistor Slope Impedance Dependent Distortion in Large-Signal Amplifiers” JAES Vol. 36, Number 4 pp. 213 (1988)


Largely forgotten during 70's, rediscovered/reinvented in 90's as complementary bipolar IC processes and current feedback op amps became popular

Hawksford's paper analyses circuit, shows near equivalence to traditional cascode, shows many topological variants with application to discrete audio amplifier design
( Hawksford may have been unaware of the Baxendall ref.)

Provides nearly 100x improvement in nonlinearity due to Hfe and collector-base impedance variation over single transistor ( Ccb cancellation gives traditional cascode's speed as well )

NOT JUST A DARLINGTON!
 

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…for even more fun see:

“A General Relationship Between Amplifier Parameters, And Its Application to PSRR Improvement” E Sackinger, J Groette, W Guggenbuhl, IEEE Trans CAS vol 38, #10 10/83 pp 1171-1181

which gives:

1/(CMRR) + 1/(PSRR+) + 1/(PSRR-) = (1/Adiff) * Zload/(Zload+Zout)

as a fundamental relationship for the standard op amp, and shows ways around this limit by adding diff output or output ref to a amp circuit

( admit it, you’ve always wanted to say: “that’s an obvious consequence of the gauge-invariance of the electric potential field” )
 
jcx:

>The Williams approach is frighteningly complex, I have prototyped and simulated this "Super Pair" cirucit but never tested it thoroughly for a product application<

I enjoy the conceptual process behind the circuit, which is a major reason why I am attracted to it. I imagine that building a circuit that incorporated similar thinking could be a useful learning experience.

Thank you for bringing my attention to the Baxandall circuit. I found it very interesting - not the least because I worked out a compound cascode circuit on my own which is almost identical to the Baxendall version that you posted. I had been under the impression that I had invented something pretty cool, but it looks like I was beaten to the punch over 30 years ago. :) It would be interesting to read Baxandall's article, because this would give me an additional perspective on my own work.

In my version, both R3 and R4 are CCSs, and I alternate between tying R4 to a independent voltage rail per your schematic, or to the Iout node in a floating configuration. My circuit exists in both NPN-PNP and PNP-NPN flavors, and I use it primarily as a cascode with built-in Cob cancellation.

I have not read the Hawksford paper either, but it looks like I should.

Additional thoughts on the compound cascode circuit. Q5 should ideally be chosen for high hfe, low Cob, but also low Vsat, and this is a somewhat unusual combination.

Although one of the goals is to cancel the Cob of Q4, the end result is a reduction rather than a cancellation. If we express the residual capacitance as Cres, the equation is:

Cres=(1-hfb)Cob,

where hfb is the current amplitude of Q5 in common-base mode, and hfe is the current amplitude of Q5 in common-emitter mode.,

This can be approximated as Cob/hfe, and since hfe is typically anywhere from 100~1000, the residual capacitance Cres will be reduced to 1% ~0.1% of the Cob.

If we also look at the output impedance, for a normal simple cascode this can be approximated as ro x hfe, where ro is the collector-to-emitter impedance - including parasitics. If we appropriate jcx's device identifiers and apply them to a simple cascode, the equation would be ro4 x hfe4.

Now if we look at the output impedance of the compound cascode, ro x hfe remains intact, but is further multiplied by the hfe of the additional transistor. In jcx's circuit, we would have (ro4 x hfe4) x hfe5, and the output impedance will go way, way up.

In practice, the output impedance of a simple cascode may be, say, 30Mohm, while the output impedance of the same device when used in compound cascode configuration will be more like 300Mohms.

regards, jonathan carr
 
The relation:

1/(CMRR) + 1/(PSRR+) + 1/(PSRR-) = (1/Adiff) * Zload/(Zload+Zout)


shows that high PSRR & CMRR is only possible in a op amp if the gain Adiff is very high, it would be interesting to know if Scott Wurcer knew this when designing the AD797

If Sy can get the attention of Analog Devices maybe he can get someone to educate Soufiane Bendaoud on this issue and prevent his buggering more of AD’s spice models by adding “CMRR” modeling parts that are referenced to ground, ruining perfectly good multipole op amp models for predicting floating/bootstrapped power supply op amp behavior – the irony is that it actually requires fewer parts to model these effects correctly

In discrete design we can do better than this relation for the PSSR by referencing the Vas stage to an external circuit reference ground by separately regulating the Vas and input stage supplies
 
To be honest such a dismissive post tends to undermine your credibility. Having re-read the thread, I believe the original poster was complaining about CMRR and PSRR modeling networks assuming ground referenced power supplies, which will not be accurate if the power supplies are not ground referenced (i.e. are floating). I think this would obviously influence the model accuracy...
 
I presume this 2 yr old thread has been bumped by Soufiane in response to a recent post of mine on Yahoo’s LtSpice usergroup:


an-138 shows a really good high frequency fit, including a peak
beyond the unity gain frequency

unfortunately even Analog Devices can't seem to manage to
institutionalize this level of excellence - frankly the spice macro
models coming out of the California group suck by any standard of
accuracy and the authors seem to be clueless about the issues
discussed in an-138

the ad8610 spice model fails to show ~20 degrees phase shift @~ 1MHz
from internal pole-zero compensation that is visible on the data
sheet gain curve – when questioned, the author added 3 poles @~ 2.5
GHz to trim the unity gain phase "accuracy" to < 1 degree - you can
see this pointless trick in the op177 [edit: op1177] listing in
http://www.edn.com/contents/images/260060.pdf ( the whole premise of
having to add psrr and cmrr "patches" comes from their ignorance of
how to properly use the an-138 macro modeling technique)


my motivation for exploring these modeling issues was an attempt to use the AD8610 spice model in a floating power supply circuit where somewhat realistic psrr/cmrr modeling is critical to stability – knowing that Boyle models totally fail in this application (and in the worst possible way – they show no sign of instability in sim when the physical circuit is hopelessly unstable) I now look inside at the spice model netlist to get an idea of the type of model I’m dealing with

http://www.analog.com/UploadedFiles/Application_Notes/48136144500269408631801016AN138.pdf

"SPICE-Compatible Op Amp Macro-Model Application Note (AN-138)

having read AN-138 I was optimistic that a world class operation like Analog Devices must be doing a great job, presumably thousands of engineers today rely on spice simulation to validate designs and often go directly to pcb in their prototyping – with customers collectively investing thousands of hours in simulation based evaluation you might expect a commensurate effort by the manufacturer in making the models as accurate as practical – or at least as good as implied in their applications literature


Soufiane’s own article: “Spice macro models increase design accuracy and reduce time to market” has the heavily ironic header: “Their usefulness depends on the degree
of their accuracy.”

http://www.edn.com/contents/images/260060.pdf

(which further exasperates me by being about op amp spice circuit modeling but not showing the full spice model circuit diagram he uses – I don’t “read” spice netlists like a schematic, communicating with circuit designers about analog circuits really should be done with circuit diagrams)

After weeks of email customer service correspondence with Soufiane I gave up on trying to get enough of his attention to get a responsive reply addressing my questions about the AD8610 macromodel (for which he was unable to supply a circuit diagram to make discussion simpler)

Talking with “the big guys” at Analog Devices Op Amp Applications seminar in Andover months later in a side-conversation I was told the Ca group was using a simplified model and that they had been asked to change it, when another AD “heavyweight” joined the conversation he was clued in to the topic’s context with the phrase “its those California guys…” by the AD presenter I was speaking with



AN-138 is the only op amp spice modeling technique published by Analog Devices I’ve seen – as a customer I might expect them to use for all of their op amps

AC psrr modeling is “native” to the an-138 modeling technique – it even handles different +/- psrr transfer functions (best thought of as ps common and diff mode gains)

Cmrr is largely determined by the input stage – here macro models use diff pair input Q models, correct sizing of these Q parameters with the addition of a few parasitic tail current source and isolation junction components should capture most of the AC cmrr performance – some DC cmrr behavior is determined by diff input Q mismatches ( - talk to Scott Wurcer )

So we have a product manager encouraging us to use his product’s spice models – and Oh, by-the-way you’ll have to “patch” them yourself for the accuracy that we – the people with the characterization data and (hopefully?)the expertise can’t be bothered to – even when we as a company say we do know how to do it right

Yes Soufiane, I am trying to embarrass you since nothing else I can do from outside seems to likely to motivate you to improve the spice models you are expecting your customers to use – to toss off poor AC fits implemented in a simplified model that happens to save you some time putting together a release package is disrespectful of the time your customers are going to spend using the models and I’m sure a bad business practice in $ terms simply for the applications guys time supporting customers “surprised” by behavior that the model should be able to capture

I don't know that his patch is incorrect for my floating supply app - I don't intend to reverse engineer a schematic from the netlist, but if the spice models comming from AD's Ca group complied with AN-138 I could be confident they would work in my application
 
RC Filters on Op Amp supply pins - PSRR

Hello,

I have a quick question for people in the know. Does adding an RC network on the supply pin of an Op Amp boost it's PSRR ?

I know it would attenuate the junk going into the pin, but does it actually improve it's PSRR ?

What if the op amp was bootstrapped also ? RC filter in a loop sort of thing...

I was thinking of an RC filter with a 3db point set at the point where the PSRR/loop gain falls with frequency.

Plus PSRR is reduced by gain also.

Advice welcome.

Kevin
 
soufiane said:
kevin, I don't think that would help your PSRR. Proper bypassing of the supplies is always helpful but as far as increasing the actual PSRR (DC), if anything an RC might screw up the resonnance of your C's

Hello,

Thanks for the reply.

What if the op amp supply pins was bootstrapped to it's output with an RC filter in the loop sort of thing... (aka. Walt Jung reg.)

Increased loop gain is the another answer just wanted to see what could be "milked" out of an RC filter! :p

Yeah I agree the R component of RC filters makes the impedance worst (a) and with varying loads (twitchy high speed op amps) versus frequency. (b)

We could load it with a CCS or high impedance mosfet to try and circumvent this. Just some thoughts.....

Cheers

Kevin.

PS. I am racking my head over a Netware OES server with some beers and on a saturday night. Depressing...

I think because it stimulates me intellectually I quite enjoy it.... nerd speak I guess. :)
 
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