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Old 22nd December 2008, 03:21 AM   #31
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never underestimate lazy Americans. I have 200 of each at home ready to match and have done some preliminary binning. I just need a good procedure to fine tune the results?
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Old 22nd December 2008, 03:26 AM   #32
EUVL is offline EUVL  Europe
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> never underestimate lazy Americans.

Never said that.

> I have 200 of each at home ready to match and have done some preliminary binning. I just need a good procedure to fine tune the results?

Then we have already given you enough hints.
Temperature stability is the key, especially for low current.
Now you know why I got these made in the first place.




Patrick
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Old 22nd December 2008, 03:41 AM   #33
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Patrick:

I can help with the North America distribution of your couplers. I'd be interested in 25 myself.

As for matching, I will be using these in a F4, which is around 6mA flowing through the pair (I think?). From what you mention, I can select Idss to be around 7.5-10mA and rough match to be around 0.5mA differential then measure Vgs at 6mA target current and select those that have same Vgs? Once I get these pairs, then I can thermally couple them and try one of your more advanced matching techniques?
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Old 22nd December 2008, 03:48 AM   #34
lineup is offline lineup  Sweden
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How about using 2N5462 as a P Channel JFET complementary to for example 2SK170BL.
They do not cost too much.

They are 40 VDS like 2SK170 and ~8-10 mA IDSS.
I have done some preamp sims using 2SK170/2N5462 .. with good results.
-- 4 JFET is complementary LTP pair input configuration
The idea is of course to get both N and P FET with 40 VDS rating.

1. Are there any major drawbacks with 2SK170BL + 2N5462 option?

2. Is there any good alternative N-JFET complement to the 2N5462?
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Old 22nd December 2008, 03:54 AM   #35
EUVL is offline EUVL  Europe
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> How about using 2N5462 as a P Channel JFET complementary to for example 2SK170BL.

They have 60 times the noise and 10% of the transconductance of the 2SJ74s.

People don't buy Toshiba JFETs in their thousands for no reasons.

The only other (small signal) JFET I use which is not Toshiba is BF862. I also use J111s and J174s, but only to cascode the Toshibas for high voltage applications.


Patrick
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Old 22nd December 2008, 03:56 AM   #36
EUVL is offline EUVL  Europe
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> I can help with the North America distribution of your couplers. I'd be interested in 25 myself.

Thanks for the kind offer.

We need two more volunteers and still 375 heatsinks to be accounted for (assuming each person take 25 minimum).


Patrick
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Old 22nd December 2008, 04:12 AM   #37
EUVL is offline EUVL  Europe
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> As for matching, I will be using these in a F4, which is around 6mA flowing through the pair

In the F4, the pair is used a follower with degeneration.

The best way to match is to apply working voltage (23V in that case, which is a lot), add the source resistor (22R ??), ground the gate, and measure Idss. I think you'll need about 8mA Idss to get 6mA bias, but the absolute value is not critical.

The heatsink is not (meant to be) a tight fit, so you need to glue the JFETs to the heatsink with thermal glue. A bit unpractical for matching.

I would just match with blank TO92 in a thermal enclosure (basically a closed box which the FET inside, with wiring running through). With 23V Vds, there is so much heat anyway that probably thermal stabilisation is easier to achieve.


Patrick
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Old 22nd December 2008, 09:01 AM   #38
AndrewT is online now AndrewT  Scotland
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Hi,
my method is based on that described by Anatech.

JIG:
Set up and LTP pair facing each other. Plug this into a 8pin DIP socket. I use a bulldog clip to hold the pair in thermal contact.

Set the source/emitter resistors to 0r0.
Set the two drain/collector resistors to 100r or 1k0 +-0.1%
Connect the gates together.
Feed the gates with a reference voltage. A 1k0 pot as the lower leg of the resistor ladder and a set of 3 parallel resistors as the upper leg of the ladder. Solder one 10k resistor in permanently. The other two (10k & 5k6) can be clipped in parallel when testing higher Idss devices. For 20+mA I used all three resistors in parallel. This arrangement allowed Idss from 2.5mA to 30mA devices to be tested and matched.
Add a 100r resistor from the pair of drain resistors to positive.
Add a 100r resistor from the combined sources to negative.
Connect a DMM1 set to 200mVdc across one drain resistor.
Connect a DMM2 set to 200mVdc across the two drains.
Turn the pot to minimum.

Measuring:
Increase the supply voltage to [Vds + voltage loss across the three supply resistors] monitor the drain current on DMM1,
adjust the pot till Idss is set. Check the difference in voltage on DMM2. This is the current difference between the two FETs when their Vgs is exactly the same. Check the total voltage across Vds, is it truly the set point your require? Adjust the power supply if necessary. This PSU voltage will be the same for all Idss test measurements. Reduce the PSU voltage for the next Id test
turn down the pot to reduce Vgs (i.e. more negative than 0Vgs).
Does DMM2 change?
Turn pot down until DMM1 reads ~70%Idss and note DMM2, adjust pot to 50%Idss and note DMM2, (for first run of measuring, stop after just three readings) adjust pot to 30%Idss and note DMM2 finally adjust pot to ~20 to 25% of Idss and note DMM2.
How much does the DMM2 reading swing for varying Id when Vds is at the test voltage?
Keep one of the FETs in place and use it as a reference. Set the other FET beside it's DMM2 readings.
Insert next FET and repeat. Take out the reference FET and it's DMM2 readings are all 0,0,0,0.
You end up with a small group of measured FETs. Look for a pair that have similar errors (DMM2 reading) across the whole range of test Id.
Pick two FETs that appear to be very close for the respective DMM2 readings. Insert into jig and retest at a variety of Id. You can go up in Id to Idss as well as down towards 20% Idss. The temperature stability is surprisingly good, because both FETs are passing almost identical currents at almost identical Vds, i.e. both are dissipating the same power and are clipped together and thus at the same, even varying, temperature.
I keep REF FET in place and check the adjacent +1%Idss and -1%Idss against the same reference.

When one finds a supermatched pair it is surprising how one can vary the PSU voltage and/or the Id (pot) and still the error voltage stays very close to zero. But I found very few supermatched pairs even over this somewhat resistricted range of 25% to 100% Idss.
I suspect an LTP of FETs in actual operation rarely if ever vary their currents outside this range if Id is set ~70% Idss. Can anyone confirm?

I'll try to sketch the jig & resistor schematic and post later.
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Old 22nd December 2008, 12:05 PM   #39
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Quote:
Originally posted by EUVL
I was never suggesting you to take 500.

But someone has to volunteer to start a GB, and we probably need 20 people each taking 25 to make it work.

I had 20 prototype made as a favour from a friend, but it was a lot of setup work that the friend who did it is not willing to do it again unless he gets his hours compensated, which is of course fair.


Patrick

Hi Patrick,

yes of course you're right
25 pcs for me.

let's see if anyone is willing to start EU GB..

Vale
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Old 22nd December 2008, 03:45 PM   #40
JimT is online now JimT  Canada
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I would want about 10. Maybe more.

Thanks
Jim
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