The next best thing to 2SK389 / 2SJ109 ?

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Lumba Ogir

Banned
Joined 2005
Hannes,
the possibilities of reducing distortion by matching are strongly limited so don`t expect much. The benefit of matching depends on topology, biasing and operational conditions. As you don`t have any control over most parameters, die design and manufacturing quality generally is more important. There is so much to do about distortions caused by other mechanisms, you should concentrate on that part instead.
 
A

aterren

Member
Joined 2008
Below are the JFET references I found after posting yesterday. Hopefully they are helpfull to others.

Alex_twn said:
Hello, there are few interesting things to read, on my side I recommend what was written by Erno Borbely or Nelson Pass.
JFETs: The New Frontier, Part 1 | audioXpress

By the way when selecting the right JFET, the best would be to have at least 7mA for Idss and when assembling the module choosing Rs that gives a current of 3.5mA.

aterren note: PDF fersions of the orginal articles are attached to this message
Click to expand...

Nelson Pass said:
Get a 5 to 13 volt supply and a DC voltmeter. Connect the +V to the
Drain, connect the Gate and Source together to a 100 ohm resistor,
and connect the other lead of the resistor to ground.

Measure the voltage across the resistor, which gives the Idss. 1 volt
= 10 mA of current.

Try to measure all devices under the same conditions, temperature,
and duration of test.
Click to expand...

EUVL said:
I use 9V Vds, which is about the optimal working point.

Low Idss take ages to stabilise thermally, as the current keeps drifting. One breath of air, and it changes by 20uA easily.

Anything above 9mA is easy. They warm up fast and remains stable over minutes.

My Idss measurements were all taken at steady state. A thermal shield from the environment will help.

And you need to do that at the same room temperature. It is therefore easier in Winter than summer, but you need to measure room temperature.

Of course if you have done a rough sreening first, and you can just match a pair right after each other to reduce those variables.

Patrick
Click to expand...


AndrewT said:
Hi,
my method is based on that described by Anatech.

JIG:
Set up and LTP pair facing each other. Plug this into a 8pin DIP socket. I use a bulldog clip to hold the pair in thermal contact.

Set the source/emitter resistors to 0r0.
Set the two drain/collector resistors to 100r or 1k0 +-0.1%
Connect the gates together.
Feed the gates with a reference voltage. A 1k0 pot as the lower leg of the resistor ladder and a set of 3 parallel resistors as the upper leg of the ladder. Solder one 10k resistor in permanently. The other two (10k & 5k6) can be clipped in parallel when testing higher Idss devices. For 20+mA I used all three resistors in parallel. This arrangement allowed Idss from 2.5mA to 30mA devices to be tested and matched.
Add a 100r resistor from the pair of drain resistors to positive.
Add a 100r resistor from the combined sources to negative.
Connect a DMM1 set to 200mVdc across one drain resistor.
Connect a DMM2 set to 200mVdc across the two drains.
Turn the pot to minimum.

Measuring:
Increase the supply voltage to [Vds + voltage loss across the three supply resistors] monitor the drain current on DMM1,
adjust the pot till Idss is set. Check the difference in voltage on DMM2. This is the current difference between the two FETs when their Vgs is exactly the same. Check the total voltage across Vds, is it truly the set point your require? Adjust the power supply if necessary. This PSU voltage will be the same for all Idss test measurements. Reduce the PSU voltage for the next Id test
turn down the pot to reduce Vgs (i.e. more negative than 0Vgs).
Does DMM2 change?
Turn pot down until DMM1 reads ~70%Idss and note DMM2, adjust pot to 50%Idss and note DMM2, (for first run of measuring, stop after just three readings) adjust pot to 30%Idss and note DMM2 finally adjust pot to ~20 to 25% of Idss and note DMM2.
How much does the DMM2 reading swing for varying Id when Vds is at the test voltage?
Keep one of the FETs in place and use it as a reference. Set the other FET beside it's DMM2 readings.
Insert next FET and repeat. Take out the reference FET and it's DMM2 readings are all 0,0,0,0.
You end up with a small group of measured FETs. Look for a pair that have similar errors (DMM2 reading) across the whole range of test Id.
Pick two FETs that appear to be very close for the respective DMM2 readings. Insert into jig and retest at a variety of Id. You can go up in Id to Idss as well as down towards 20% Idss. The temperature stability is surprisingly good, because both FETs are passing almost identical currents at almost identical Vds, i.e. both are dissipating the same power and are clipped together and thus at the same, even varying, temperature.
I keep REF FET in place and check the adjacent +1%Idss and -1%Idss against the same reference.

When one finds a supermatched pair it is surprising how one can vary the PSU voltage and/or the Id (pot) and still the error voltage stays very close to zero. But I found very few supermatched pairs even over this somewhat resistricted range of 25% to 100% Idss.
I suspect an LTP of FETs in actual operation rarely if ever vary their currents outside this range if Id is set ~70% Idss. Can anyone confirm?

I'll try to sketch the jig & resistor schematic and post later.
Click to expand...
 

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