hi-loop gain amp

[mfc]

The higher bias reduces all the higher harmonics (H3...)
at 20Khz. Attached is a FFT at 45Vout into 4ohm.

The second is down 126db below the fundamental, and
the other harmonics are 20db below that.

THD at this level was .5ppm

[mfc]

Finally,

It looks like it also helped increase the slew rate.

Attached is a 100Khz square wave 45Vout into 4ohm.
Not a world record, but certainly fast enough.

Thanks!

[Lumba Ogir]

Mike,
looks much better to me, I would increase the current in Q18 by changing the value of R37/44 to say 330Ohm.
Do you have a link to a data sheet for ECX10N18?

[mfc]

Originally posted by Lumba Ogir
Do you have a link to a data sheet for ECX10N18?

The darn data sheet is too big. Send me your email and I'll
send you a datasheet. I'm using the EC20N20/20P20 which is
the same thing just a little bigger.

A 2SK1058/2SJ162 woud do as well, although R42 and the
gate stoppers might need a little tweaking.

Thanks,

Mike

I'll play around with tweaking the current on the input CFP
transistors.

[Bob Cordell]

Originally posted by darkfenriz
Keep in mind that mosfets in reality are only slightly faster than bipolars.

I have to diagree a bit.

In most cases vertical power MOSFETs are much faster than even RET BJTs. This is not so much the case for Lateral MOSFETs, to which you might have been referring.

The NJL3281 RET BJT has a peak ft of 50 MHz at 2A, but this falls to 20 MHz at a typical 100 mA bias point. It also suffers from ft droop at high collector current, as do virtually all BJTs. Its ft falls to 20 MHz at a collector current of 5A with 5V collector to emitter. It falls below 5 MHz at a collector current of 10A.

The IRFP240 has an ft of 74 MHz at a typical bias current of 150 mA. Its ft gets up to about 300+ MHz at currents above 1 amp.

Collector-base capacitance for the NJL3281 is about 400 pF at a reverse voltage of 5V, while the IRFP240 drain-gate capacitance is on the order of 500 pF at a drain-source voltage of 5V.

Cheers,
Bob

[darkfenriz]

Hi Bob

I was refering to a device made 'dead stable' on any occasion. In my experience using bjts makes things easier to stabilize, so that you often end up with a mosfet stage only slightly faster then similar bjt stage.
I know you were using some nice snubbers to squeeze out more speed and achieve good stability, but that's still a trick, isn't it?

Regards,
Adam

[Bob Cordell]

Originally posted by darkfenriz
Hi Bob

I was refering to a device made 'dead stable' on any occasion. In my experience using bjts makes things easier to stabilize, so that you often end up with a mosfet stage only slightly faster then similar bjt stage.
I know you were using some nice snubbers to squeeze out more speed and achieve good stability, but that's still a trick, isn't it?

Regards,
Adam

Hi Adam,

You make a good point. MOSFETs, largely due to their higher ft, do have a greater tendency to local parasitic oscillations. Indeed, in this regard, they sometimes require more skill to apply, especially if their full potential is to be realized. I do cringe a little when I see big gate resistors used to stabilize them. BTW, gate stopper resistors used with BJTs also tend to have the same effect.

A related speed issue is the amount of current that one has to pull out of the base or gate of a heavily turned-on devive to turn it off or to cause it to slew at a given rate of current change. The MOSFETs tend to do better than BJTs in this regard as well.

Cheers,
Bob

[mfc]

Using a clue from OStripper (thanks), here is better front-end
performance then what was there before.

This tweaks the values of the specified resistors to all but
eliminate 2nd and 3rd order distortion components.

Total THD 20Khz into 4ohm 45v peak = 0.00001%
or > .1ppm.

The current through the NPN/PNP transistors are close to
the same 1.8ma/2.1ma. You may recall, I increased the
current in the LTP to improve the slew rate.

I know it will never be this good in reality.

Mike

[andy_c]

Here's a few questions:

What happens to the collector current of Q7 when in the positive half cycle of clipping, and why? How do you fix it? (Make sure you overdrive it enough in the sim to check this).

You'll also need a real current source for the VAS in order to look at clipping for the negative half cycle. With an ideal current source here, it's more of a concept than a design. Of course, input stage current sources are a non-problem, so this statement doesn't apply there. But the VAS current source is critical and a key part of the design.

[mfc]

Originally posted by andy_c
Here's a few questions:

What happens to the collector current of Q7 when in the positive half cycle of clipping, and why? How do you fix it? (Make sure you overdrive it enough in the sim to check this).

You'll also need a real current source for the VAS in order to look at clipping for the negative half cycle. With an ideal current source here, it's more of a concept than a design. Of course, input stage current sources are a non-problem, so this statement doesn't apply there. But the VAS current source is critical and a key part of the design.

Hi Andy,

I haven't found either of the current sources to be too critical to
this.

But yes, the picture during clipping look a little ugly...

I find the problem originates with the driver (MOSFET) around
a Vin of 3.959v.

It plays havoc with the VAS current demands.

Couple of thoughts to help the VAS with recovery...

1) Remove the VAS current source entirely and replace it with a
bootstrap consisting of two 4K resistors and a 2.2uF cap.
Replace the VAS current source with the two 4K resistors.
Connect the 2.2uF cap between the junction of the 4K resistors
and the output.

2) Add local feedback resistors of ~50K between the gate and
drain of the driver FETs. This helps the VAS momentarily
keep up with the current demands on it.

I like 2) because it also improves the driver linearity during
normal operation by providing local feedback.

What are your thoughts?

Thanks,

Mike