measurements for lineup, more on distortion cancellation
Rainy Friday so I tried this configuration in further exploring distortion cancellation in simple FET circuits. Maybe too many new things going on at once. The idea was 1) Use a diode to generate enough voltage at the source so that you don't need bypassing (diode dynamic resistance is very low) or a separate negative bias voltage for the gate. .6 volts or so catches a huge portion of the 2SK170 population. Furtermore from the basic physics a diode has sqrt(2*q*I) noise current yielding -3dB the noise of the dynamic resistance (in theory). I'm sure 1N4148's have something bad going on at low frequencies but one could diode connect a low noise transistor instead. 2) Cascode with a high Vp FET to get as much gm as possible while still having enough action at the drain to get the distortion cancellation. Also, in theory, this would greatly reduce the supply sensitivity. Results are pictured.
The difference is 1.5mA vs 1.625mA bias, less than 10% operating point for almost 30dB reduction (output level is 3V p-p @ a gain of ~24dB). I have removed some harmonically unrelated switching supply noise because I am not in a low noise environment and I'm just hacking around anyway. Notice though the supression of second order intermods on the fundamental including the very fine spread very close in. This stuff is mixed in at the input due to my bench setup not on the supply. This would be the equivalent of lows in the input signal. Considering the frequency balance in a typical RIAA stage this could have interesting implications.
Again I have not made an exhaustive survey so if it's old news at least it's not bad news.
"The question of who is right and who is wrong has seemed to me always too small to be worth a moment's thought, while the question of what is right and what is wrong has seemed all-important."