The Frugalamp by OS

[MJL21193]

.MODEL 2SA1381 pnp
+IS=5.5544e-14 BF=148 NF=1 VAF=580
+IKF=0.2163 ISE=2.0546e-15 NE=1.5 BR=1.892
+NR=1 VAR=100 IKR=0.187544 ISC=2.04807e-09
+NC=1.5 RB=10.18 IRB=2.0e-6 RBM=0.02
+RE=0.62 RC=3.572 XTB=0.907 XTI=3
+EG=1.206 CJE=9.572e-12 VJE=0.748 MJE=0.371
+TF=8.0312e-10 XTF=1 VTF=10 ITF=0.01
+CJC=1.147e-11 VJC=0.541 MJC=0.329 XCJC=0.9
+FC=0.5 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1


.MODEL 2SC3503 NPN
+ IS =2.0893E-14 BF =101.5 NF =1.0 BR =7.655
+ NR =1.007 IBC =2.0893E-14 IBC =2.0893E-14
+ ISE =4.3652E-14 NE =1.5 ISC =1.2598E-9
+ NC =2.0 VAF =717.25 VAR =13.16 IKF =0.2512
+ IKR =0.0832 RB =2.98 RBM =0.001 IRB =0.001
+ RE =0.5305 RC =0.9 QCO =0.05 RCO =50.1187
+ VO =2.476 GAMMA =1.8231E-7 CJE =6.6039E-11
+ VJE =0.7017 MJE =0.3253 FC =0.5
+ CJC =6.6072E-12 VJC =0.5 MJC =0.2439
+ XCJC =0.6488 XTB =1.4089 EG =1.2129
+ XTI =3.0


http://www.fairchildsemi.com/models/PSPICE/Discrete/Bipolar_Transistor.html

 

[ostripper]

Thanks MJL, now with these devices I have way too much OLG,
working from the other end of the stick as to say..

time to reduce the load..
BTW the amp simmed perfectly 1st time but wow what a output
swing...(clipped like hell)
OS

 

[ostripper]

It works , but had to degenerate everything...GAIN CITY..
here it is with its plots..

An externally hosted image should be here but it was not working when we last tested it.

Finally got VAS to stay class A with degen of r3/25/10 (red/green
in plot below), reduced load on diff.(light blue/ purple) and the dark blue widlar buffer keeping it all nice and balanced (at bottom
of plot)

An externally hosted image should be here but it was not working when we last tested it.

then the gain plot...

An externally hosted image should be here but it was not working when we last tested it.

back to work
OS

 

[jaycee]

I'm back to looking at this kind of VAS stage now. It seems to have been used in a number of great sounding circuits so there must be something to it

Also I like the "balanced" idea, both halves of the LTP being referenced by the VAS to control the signal.

One thing I have started looking at, is the Cyrus One circuit, specifically the input stage. I had been playing around with CFP input stages, and the Cyrus one seems to sim very well indeed - plus the Cyrus One is an excellent sounding amplifier. I have a friend who isn't even an audiophile, but he swears by his old Cyrus One over anything recent.

 

[ostripper]

Since andy C. showed me the loop gain test I have pondered its
relevance. Besides the importance of the amps unity gain
point and phase margin what I really wanted to know was
whether stability (oscillations)could be predicted from the data.
I think the answer is here,,,,

An externally hosted image should be here but it was not working when we last tested it.

The full article here..
http://www.analogzone.com/acqt0131.pdf

A good rule of thumb as most DIY amps , my amps, and
the new one fall by only 15-20 db/decade , which seems to
mean stability...

OS

 

[homemodder]

Hi jaycee

Your friend is right the cyrus is very good sounding amp, far better than many modern designs. A mod I did some years back for someone was to use Jfet cfp instead, that is if you like the sound of jfets. More warmts and weight in mid and low frequency. That design can be futher improved by having a second vas taken from the first vas s second transistor emiter and operating at higher current. This way the output has no significant influence on the vas. Try designing something around this, youll be very happy with the results.

Alex

 

[jaycee]

it is but the circuit is an absolute dog to stabilise. The input stage has crazy amounts of gain and the closed loop response goes out to ~1MHz before reaching 0dB. Cyrus have a triple output stage with the predrivers loaded with a heavy capacitance to prevent this.

 

[jaycee]

With regard to phase/gain plots, I suspect I have been using a duff technique. What I do is plot V(A)/V(B). The gain needs to be 0dB before the phase drops below 0 degrees. There needs to be some margin so generally if it drops below 70 degrees it's going unstable. This seems to have worked well for me so far, but it could be totally and utterly wrong.

 

[homemodder]

Jaycee. try a rc accross ltp collectors. Have a look at using phase lead in cobination with miller too, does wonders.

 

[andy_c]

With regard to phase/gain plots, I suspect I have been using a duff technique. What I do is plot V(A)/V(B). The gain needs to be 0dB before the phase drops below 0 degrees. There needs to be some margin so generally if it drops below 70 degrees it's going unstable. This seems to have worked well for me so far, but it could be totally and utterly wrong.

It turns out the technique in the LTspice audioamp.asc is only an approximation of the loop gain. It's a good approximation if your floating voltage source is placed in the same location as in audioamp.asc, but if it's put in other locations it may give completely wrong results.

An exact method is shown in the loopgain2.asc file in the LTspice educational directory. To use this method, you can use F6 to copy the voltage and current sources Vi and Ii into your schematic, and Ctrl-v to paste. When you do this, LTspice will rename the reference designators to something like Vi1 and Ii1, so you'll need to change them back to Vi and Ii. If you have other existing sources named Vi or Ii, you'll need to rename them too. Also, if you have existing nodes named "x", you'll need to rename them as well, as SPICE considers nodes with the same names to be shorted together. Then put two SPICE directives in your schematic like so:

.step param prb list -1 1
.param prb 0

Use the first for loop gain sims and comment the second out. For normal sims, do the opposite. I usually copy the messy loop gain formula and make it a comment in my schematic so I can paste it in as a plot expression when needed.

The standard textbooks on feedback amps do an interesting analysis, making an approximation that the loop gain has two poles only. The result is that overshoot and/or ringing will occur for phase margins less than 78 degrees. That's why I shoot for 80 degrees phase margin (phase shift of -100 degrees) and is why I gave that number to OS earlier in the thread.

Another interesting thing to try is to look at phase margin with a capacitive load. That's why people use output inductors .

 

[jaycee]

Great stuff. Thanks!
This probably explains why I have had schemes where my trivial phase/gain check has told me the design should be stable, yet when i sim it with a small enough time step, it oscillates.

Pity my Core2Duo system is out of action at the moment or I would be having a throroughly good play with this!

 

[ostripper]

WOW, I'm drowning in knowledge now....

Pity my Core2Duo system is out of action at the moment or I would be having a throroughly good play with this!

I glitched (core duo)a movie while doing this sim (processor hog).
but , here it is...Don't quite know how to interpret it...

An externally hosted image should be here but it was not working when we last tested it.

All this simulation is tiring, must build something ,I already laid
out the board with extra pads for compensation.(cross my
fingers)..
Final schema... simulated it to DEATH,seems to perform much
better than a standard "blameless", especially at HF.

An externally hosted image should be here but it was not working when we last tested it.

By andy C. - The standard textbooks on feedback amps do an interesting analysis, making an approximation that the loop gain has two poles only. The result is that overshoot and/or ringing will occur for phase margins less than 78 degrees. That's why I shoot for 80 degrees phase margin (phase shift of -100 degrees) and is why I gave that number to OS earlier in the thread

This is the statement that "tidal waved" me..???
how would you apply that statement to this plot??
OS

 

[andy_c]

This is the statement that "tidal waved" me..???
how would you apply that statement to this plot??
OS

It looks about right: about -100 deg phase shift at the unity loop gain frequency (around 600 kHz in this case).

So, if you were to set C2 to zero and look at small-signal square waves (say, 1V p-p at the output), you should see no overshoot. Making the phase margin worse than this should start to show overshoot and/or ringing in that test.

 

[ostripper]

Set sqaure wave in a normal sim..?
what would be a typical setting for the [v] , [t] variables,
also [Ncycles]

would I also set up a LCR at the output to simulate a "real world"
load??
OS

 

[andy_c]

If you take into account the input divider, your amp has a gain of 33. So for 1 V p-p output, the amplitude of the input square wave should be 1/33 V ~ 0.03V.

Set up the sim for transient. Set the input voltage type to "pulse" with Vinitial = 0, Von = 0.03, Tdelay = 0, Trise = 1n, Tfall = 1n. If you leave Trise and Tfall blank, it will default to a long rise time, hence the 1n for each.

Assume a 20 kHz square wave. Period = 1/20e3 = 5e-5. So Tperiod should be 5e-5 and Ton should be 2.5e-5 (for 50 percent duty cycle, ignoring the 1n rise and fall times). Leave NCycles blank. Say you want to run 5 cycles. Then set the end time for the sim to 5 * the period, or 2.5e-4.

This will give you a DC offset square wave at the input and output. You can get rid of the offset by playing around with the Vinitial of the source. However, if you make Vinitial anything other than zero, it will mess with your operating point for DC and AC analysis, so beware!

Then see the output square wave at the junction of R22 and R23, which should go roughly from 0 to 1 Volt. Set C2 to something very small like 0.0330p (so you won't have to delete it).

 

[jaycee]

I glitched (core duo)a movie while doing this sim (processor hog).

If you are using the new LTSPICE IV, it is multithreaded and will use both cores. This is a HUGE improvement over LTSPICE III which was single threaded only.

My current system is down because the Crucial Ballistix ram that I bought has failed and needs to be returned. One stick is usable at slower CAS settings, but because they are part of a kit, I have to RMA them both. Fortunately Crucial has agreed to exchange it for their standard product. I won't be buying from the Ballistix range again!

I'm really itching now. I've got two heatsinks from the Teac, and 4 pairs of MJL4281/4302 hanging about. That would only let me build one channel, but I could easily buy more once one channel is proven! I also have some MJL21193/4's in case I break something

 

[jaycee]

This will give you a DC offset square wave at the input and output. You can get rid of the offset by playing around with the Vinitial of the source. However, if you make Vinitial anything other than zero, it will mess with your operating point for DC and AC analysis, so beware!

Here is what I do. I set up one voltage source to swing from negative to positive, say Vinitial -1 to Von 1, producing the square as you describe. Then, I have another voltage source in series, whose Vinitial is 1, and Von 0. Set the rise and fall times, but no Ton or Tperiod. This cancels the square wave's Vinitial of -1 and allows the operating point to be stable. When you do any other type of wave input, you can set this second voltage source to 0 and it is ignored.

 

[ostripper]

Got it,first at small Vin(.03v).. nice square w/no ringing.
Jumped it up to
the "breaking point" +/-.771v (1.44v) saw a little ringing in the vas at "switchpoints" but never at OP . AT 1.2 V , all is good
front to back.

BTW.. under 1uS at a 90V voltage rise w/47pF Cdom.
time to build..can always tweak comp. on the "real thing"..

By jaycee -My current system is down because the Crucial Ballistix ram that I bought has failed and needs to be returned. One stick is usable at slower CAS settings, but because they are part of a kit, I have to RMA them both. Fortunately Crucial has agreed to exchange it for their standard product. I won't be buying from the Ballistix range again!

I have the oldest C2D (1.86Ghz 6320) don't bother with OC
or other BS, 1gig corsair 800mhz standard dual channel memory..
3 years ABSOLUTE
reliability and stability , all those fancy names on RAM ,what BS
RAM was very expensive when I bought it ,..120us$.
OS

 

[andy_c]

Oops, sorry. Didn't mean to torture you with more sims when you're ready to build. Was just trying to demonstrate the relationship between phase margin and overshoot for small-signal square waves. If you were to cut the comp cap in half, for example, you'd see degraded phase margin and overshoot/ringing on the small-signal square wave.

As you increase the square wave amplitude, other effects come into play, such as capacitances changing as a function of voltage, so the relationship between phase margin and transient response will no longer apply.

 

[ostripper]

It wasn't bad .Andy , I almost had to crash the Sim (1.5V) to
see any effect In the VAS (tiny, not even gross , overshoot).

As I had FA2's "little brother", mike B's "symasym" ,to compare
to I knew this amp should be a good one.
In fact , this one does better at HF and is more balanced
(thanks to the 3T widlar) than my symasym simulation.
thank you ANDY, MJL..etc. I think I will have at top quality amp
with proper layout and parts.

PS .. will post the"frugal" layout soon (PCB on graphpaper).
OS