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Old 26th November 2008, 01:18 PM   #181
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.MODEL 2SA1381 pnp
+IS=5.5544e-14 BF=148 NF=1 VAF=580
+IKF=0.2163 ISE=2.0546e-15 NE=1.5 BR=1.892
+NR=1 VAR=100 IKR=0.187544 ISC=2.04807e-09
+NC=1.5 RB=10.18 IRB=2.0e-6 RBM=0.02
+RE=0.62 RC=3.572 XTB=0.907 XTI=3
+EG=1.206 CJE=9.572e-12 VJE=0.748 MJE=0.371
+TF=8.0312e-10 XTF=1 VTF=10 ITF=0.01
+CJC=1.147e-11 VJC=0.541 MJC=0.329 XCJC=0.9
+FC=0.5 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1


.MODEL 2SC3503 NPN
+ IS =2.0893E-14 BF =101.5 NF =1.0 BR =7.655
+ NR =1.007 IBC =2.0893E-14 IBC =2.0893E-14
+ ISE =4.3652E-14 NE =1.5 ISC =1.2598E-9
+ NC =2.0 VAF =717.25 VAR =13.16 IKF =0.2512
+ IKR =0.0832 RB =2.98 RBM =0.001 IRB =0.001
+ RE =0.5305 RC =0.9 QCO =0.05 RCO =50.1187
+ VO =2.476 GAMMA =1.8231E-7 CJE =6.6039E-11
+ VJE =0.7017 MJE =0.3253 FC =0.5
+ CJC =6.6072E-12 VJC =0.5 MJC =0.2439
+ XCJC =0.6488 XTB =1.4089 EG =1.2129
+ XTI =3.0


http://www.fairchildsemi.com/models/...ransistor.html
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Old 26th November 2008, 01:28 PM   #182
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Thanks MJL, now with these devices I have way too much OLG,
working from the other end of the stick as to say..

time to reduce the load..
BTW the amp simmed perfectly 1st time but wow what a output
swing...(clipped like hell)
OS
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Old 26th November 2008, 04:26 PM   #183
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It works , but had to degenerate everything...GAIN CITY..
here it is with its plots..
Click the image to open in full size.

Finally got VAS to stay class A with degen of r3/25/10 (red/green
in plot below), reduced load on diff.(light blue/ purple) and the dark blue widlar buffer keeping it all nice and balanced (at bottom
of plot)
Click the image to open in full size.

then the gain plot...
Click the image to open in full size.

back to work
OS
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Old 26th November 2008, 09:16 PM   #184
jaycee is offline jaycee  United Kingdom
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I'm back to looking at this kind of VAS stage now. It seems to have been used in a number of great sounding circuits so there must be something to it

Also I like the "balanced" idea, both halves of the LTP being referenced by the VAS to control the signal.

One thing I have started looking at, is the Cyrus One circuit, specifically the input stage. I had been playing around with CFP input stages, and the Cyrus one seems to sim very well indeed - plus the Cyrus One is an excellent sounding amplifier. I have a friend who isn't even an audiophile, but he swears by his old Cyrus One over anything recent.
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Old 27th November 2008, 12:36 AM   #185
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Since andy C. showed me the loop gain test I have pondered its
relevance. Besides the importance of the amps unity gain
point and phase margin what I really wanted to know was
whether stability (oscillations)could be predicted from the data.
I think the answer is here,,,,
Click the image to open in full size.

The full article here..
http://www.analogzone.com/acqt0131.pdf

A good rule of thumb as most DIY amps , my amps, and
the new one fall by only 15-20 db/decade , which seems to
mean stability...

OS
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Old 27th November 2008, 08:52 AM   #186
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Hi jaycee

Your friend is right the cyrus is very good sounding amp, far better than many modern designs. A mod I did some years back for someone was to use Jfet cfp instead, that is if you like the sound of jfets. More warmts and weight in mid and low frequency. That design can be futher improved by having a second vas taken from the first vas s second transistor emiter and operating at higher current. This way the output has no significant influence on the vas. Try designing something around this, youll be very happy with the results.

Alex
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Old 28th November 2008, 10:43 AM   #187
jaycee is offline jaycee  United Kingdom
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it is but the circuit is an absolute dog to stabilise. The input stage has crazy amounts of gain and the closed loop response goes out to ~1MHz before reaching 0dB. Cyrus have a triple output stage with the predrivers loaded with a heavy capacitance to prevent this.
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Old 28th November 2008, 11:49 AM   #188
jaycee is offline jaycee  United Kingdom
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With regard to phase/gain plots, I suspect I have been using a duff technique. What I do is plot V(A)/V(B). The gain needs to be 0dB before the phase drops below 0 degrees. There needs to be some margin so generally if it drops below 70 degrees it's going unstable. This seems to have worked well for me so far, but it could be totally and utterly wrong.
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Old 28th November 2008, 12:53 PM   #189
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Jaycee. try a rc accross ltp collectors. Have a look at using phase lead in cobination with miller too, does wonders.
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Old 28th November 2008, 03:30 PM   #190
andy_c is offline andy_c  United States
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Quote:
Originally posted by jaycee
With regard to phase/gain plots, I suspect I have been using a duff technique. What I do is plot V(A)/V(B). The gain needs to be 0dB before the phase drops below 0 degrees. There needs to be some margin so generally if it drops below 70 degrees it's going unstable. This seems to have worked well for me so far, but it could be totally and utterly wrong.
It turns out the technique in the LTspice audioamp.asc is only an approximation of the loop gain. It's a good approximation if your floating voltage source is placed in the same location as in audioamp.asc, but if it's put in other locations it may give completely wrong results.

An exact method is shown in the loopgain2.asc file in the LTspice educational directory. To use this method, you can use F6 to copy the voltage and current sources Vi and Ii into your schematic, and Ctrl-v to paste. When you do this, LTspice will rename the reference designators to something like Vi1 and Ii1, so you'll need to change them back to Vi and Ii. If you have other existing sources named Vi or Ii, you'll need to rename them too. Also, if you have existing nodes named "x", you'll need to rename them as well, as SPICE considers nodes with the same names to be shorted together. Then put two SPICE directives in your schematic like so:

.step param prb list -1 1
.param prb 0

Use the first for loop gain sims and comment the second out. For normal sims, do the opposite. I usually copy the messy loop gain formula and make it a comment in my schematic so I can paste it in as a plot expression when needed.

The standard textbooks on feedback amps do an interesting analysis, making an approximation that the loop gain has two poles only. The result is that overshoot and/or ringing will occur for phase margins less than 78 degrees. That's why I shoot for 80 degrees phase margin (phase shift of -100 degrees) and is why I gave that number to OS earlier in the thread.

Another interesting thing to try is to look at phase margin with a capacitive load. That's why people use output inductors .
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