Fortuitous distortion null in simple FET circuit - Page 2

Nelson Pass · 18th November 2008, 04:11 AM

The ZV9 aka F3 uses this by trimming the cascode voltage for an
LU1014 power Jfet. With a single stage you can get it to do .003%
at 1 watt, and the null holds pretty well without thermal compensation.

And yes, the sim examples I've seen don't seem to do a good job of
predicting the distortion I see with real Jfets.

john curl · 18th November 2008, 09:15 AM

There was an AES preprint from a LA convention in the late 60's by an engineer from a middle European country, who did this sort of cancellation with bipolar transistors. It might be useful to find this paper, for the mathematics, if nothing else.

tschrama · 18th November 2008, 11:27 AM

similar I guess like we discussed here:

post 497

and here

post 577

and here

post 581

that worked very well indeed!

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18th November 2008, 04:11 AM	#11
Nelson Pass The one and only Join Date: Mar 2001	The ZV9 aka F3 uses this by trimming the cascode voltage for an LU1014 power Jfet. With a single stage you can get it to do .003% at 1 watt, and the null holds pretty well without thermal compensation. And yes, the sim examples I've seen don't seem to do a good job of predicting the distortion I see with real Jfets.

18th November 2008, 09:15 AM	#12
john curl diyAudio Member Join Date: Jul 2003 Location: berkeley ca	There was an AES preprint from a LA convention in the late 60's by an engineer from a middle European country, who did this sort of cancellation with bipolar transistors. It might be useful to find this paper, for the mathematics, if nothing else.

18th November 2008, 11:27 AM	#13
tschrama diyAudio Member Join Date: Jul 2001 Location: The Netherlands	similar I guess like we discussed here: post 497 and here post 577 and here post 581 that worked very well indeed!

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