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#11 | |
Account disabled at member's request
Join Date: Jan 2006
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Quote:
I'd add a CMCL (common mode control loop) so that it could actually work first. Suppose that the N channel “LTP” is made with perfectly matched parts; the quiescent currents in each leg are perfectly balanced with both differential inputs (+/-) at 0V. Now suppose that the P channel “LTP” parts are not perfectly matched; the currents in each leg are only equal when there is a +2mV DC offset voltage applied to the differential inputs. Now what happens when the NFB loop attempts to steer this P channel “LTP” into balance? – the N channel “LTP” is thrown way out (due to the huge DC gain 2mV input is much more than enough to overdrive the second stage). Cheers, Glen |
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#12 | |
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Join Date: Jan 2006
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Quote:
Hi The VAS is not where I see the problem - it's with the required balance of the complementary first stage. I'm pretty sure I've got it right. I explained the issue in another post prior to your reply above, which hasn't appeared yet as my posts are under moderation. I suspect it will appear at the same time as this one. ![]() Cheers, Glen |
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#13 |
diyAudio Member
Join Date: Oct 2003
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Scott,
Very nice circuit, but would be difficult to fit into a DIP8 footprint ?? This was my attempt and I had a hard time fitting in 7 active devices (SOT23) : http://www.diyaudio.com/forums/showt...445&highlight= Perhaps you would also come up with one using (less no.of) SMD components, such as BF862, etc. ?? Best regards, Patrick |
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#14 |
diyAudio Member
Join Date: Jan 2004
Location: dorchester ma
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A little egg left on my face this morning. Glen you are somewhat right. I'm not set up for Monte Carlo at discrete tolerances. The circuit is surprisingly robust to IC tolerances after laser trim, but a discrete would require a few trim pots or offset servo.
You would think there was no tolerance at all but .1-.2% shifts seem Ok, this is orders of magnitude worse than I am used to. Before I went over the cliff to this totally symetrical design I was working on something Friday that would be more discrete friendly. I'll resurect it. Forgive a little Sunday whiteboarding. ![]()
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#15 | ||
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Join Date: Jan 2006
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Quote:
Quote:
EDIT: After doing some calculator button pushing I think you might be saved from the need of a CMCL. The VAS which does not have emitter degeneration and is not preceeded with a EF buffers to lighten the load on the input stage keeps the input stage gain down. The low gm of the Jfet input pairs also helps things here. I think it might still be touchy though WRT to "offset fight". In my experience with circuits like these a maximum gain of about 40dB can be had from the first stage - but matched dual-die / array input devices and resistor trimming to null out the offsets is critical to keep the whole amplifier well balanced. If you really want more than 40dB of first stage gain then a CMCL is pretty much mandatory - like in Edmonds PGP amp. How much DC gain does the simulator give you for the first stage? I'd add a mV voltage source in series with one of the input jfet source pins to simulate a realistic Vgs mismatch and check the quiescent currents in all legs (LTP/VAS) of the amplifier to see just how much the balance is thrown out. Cheers, Glen |
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#16 |
diyAudio Member
Join Date: Jan 2004
Location: dorchester ma
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Glen, thank's again for your comments. It looks like a simple gain killer for the first stage (2K 's across the drains of the FETs) seems make the offset pretty robust without much compromise to the circuit. A simple offset trim should do now.
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"The question of who is right and who is wrong has seemed to me always too small to be worth a moment's thought, while the question of what is right and what is wrong has seemed all-important." |
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#17 | |
Account disabled at member's request
Join Date: Jan 2006
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Quote:
I almost suggested resistive drain loads, but I wasn’t sure how prepared you’d be to super-match jfet pairs ![]() However this leads to a quandary; If it transpires that a 2k load resistance is necessary to mitigate offset imbalance how do you justify the extra complication of those current source input stage loads? ![]() Glen |
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#18 | |
diyAudio Member
Join Date: Jan 2004
Location: dorchester ma
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Quote:
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"The question of who is right and who is wrong has seemed to me always too small to be worth a moment's thought, while the question of what is right and what is wrong has seemed all-important." |
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#19 |
diyAudio Member
Join Date: Sep 2006
Location: Graz, Austria
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Looks very interesting, Scott!
Looking forward to your results! Have fun, Hannes
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#20 |
diyAudio Member
Join Date: Jan 2006
Location: Daegu,ROK
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Patrick,
Abot absolute DC offset and speaker protection on aleph-x... I found this for balanced speaker protection circuit on aleph-x thread. IF this operate when absolute DC offset several volts, I mean that realy is on position at high absolute DC offset... I have to use this circuit. But I can't read exact zener value and constant current IC. Please let me know. Regards, Chois |
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