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Old 20th October 2008, 02:05 PM   #1
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Default JFET CS design, how? (and possible SPICE oddity)

Alright, so I'm trying to design a regular JFET common source amplifier stage with a voltage gain of +20 dB (or rather two consecutive ones for a gain of +40dB with a pot between them, but that's not the issue), using the J201 transistor. Should not be impossible, right? Problem is, I've heard and read at least three different methods of selecting the resistances, and none of them are free from troubles.

(This is the standard CS stage I'm talking about, just so we all have the same definitions)

The first one is the "replace a tube with a JFET" thing, which fixes RS and adjusts RD until the drain voltage is about half of VDD. This, however, doesn't give much control over the drain current and therefore the gain.

Another method suggests to do the exact opposite: Select RD based on the desired ID and then adjust RS until the drain voltage is halfway between VGS(off) and VDD. This sounds better, but refuses to work for me.

The third one is http://www.electronics-tutorials.ws/...ier/amp_3.html which I stumbled upon trying to find a solution to my problem with #2, but by the biasing alone, I dismiss that one straight away.

So my question is: what is the proper, working way to design a JFET common source amplifier stage for a specific gain?

Also, my problem with number two might be a SPICE one (MacSpice 3f5 specifically). Even if I use circuits that others have used with good results, such as this one, an op simulation will give me what seems to me like rather odd results. For the circuit linked to, my drain voltage sits snugly at 7.9V, hardly a recipe for good performance. By the second method mentioned above, I have to decrease RS all the way to 180 ohms before the drain voltage is where it should be. Is this problem familiar to anyone, and if so, is there a way to circumvent it?

(no, I haven't tried it on a breadboard instead of SPICE, my components are in an entirely different part of the world than I am at the moment)
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Old 20th October 2008, 02:58 PM   #2
lineup is offline lineup  Sweden
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whatever ID you want
and whatever method you use to get there
the JFET of your choice must be able to provide this current

also you the RD should be chosen to match you load R
because unless you use some output buffer follower
the load Impedance will be parallell to RD, for AC signals

You can have a look at Nelson Pass JFET BOZ
it is one single JFET preamplifier

The chosen JFET is arranged for best performance
into a specific load impedance/resistance

Schematic.
http://www.diyaudio.com/forums/attac...amp=1181083159

Topic:
Jfet BOZ
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Old 21st October 2008, 10:01 AM   #3
h_a is offline h_a  Europe
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Hi Stefan,

the 2N5484 has 5 times the transconductance than your J201 part. That means already that you need 5 times the load resistance to get the same gain. That in combination with a decent current is not possible with +15V supply rails.

Have fun, Hannes
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Old 21st October 2008, 03:59 PM   #4
h_a is offline h_a  Europe
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Hi Stefan,

I have now a bit more time for a reply.

Getting that common source stage into shape is not so hard; look up the equation for voltage gain in the wikipedia. You'll see it depends on transconductance, Rs and Rd.

First of all, Rd sets the gain, Rs reduces gain and is not strictly necessary. The reason why it's used is to reduce distortion. See Erno Borbely's articles for that (E. Borbely, Jfets - the new frontier 1+2).

So first calculate what Rd you need for a specific gain (without Rs as a start); with a 15V rail you will find that there's an upper gain limit, as the bigger you make Rd the larger the voltage drop across it (current is about IDSS). If you want e.g. 8V across the jfet, that leaves only 7V for Rd at IDSS. As IDSS is say 10mA, your Rd is already limited to 700 Ohm.

You have 2 choices then: increase rail to be able to increase Rd or get a jfet with higher transconductance. Both have limits.

For Rs you have to sacrifice gain in favour of better distortion performance, but I refer you again to Borbely for the details.

Hope that helps - have fun, Hannes
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Old 23rd October 2008, 10:24 AM   #5
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The first circuit I linked to was meant to show the general layout I was referring to, not the actual values. Sorry if that was a bit unclear. Also, my problem is rather with getting sufficiently low gain, rather than the other way around.
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