CFP oscillation woes

[ian_elvar]

Help. I've got a whole load of BUZ90xD's and I'm trying to build fairly conventional 3 stage circtuit to use them in. I've been trying a CFP output, but all I can seem to make are the worlds most ferrocious RF oscillators! I don't know whether it's the design that's at fault (I've tried many!), my PCB layout (I've tried many), or whether this just isn't going to happen and I should be looking to do something different. I'm up for experimentation, and learning by making mistakes and working out what went wrong, but I've run out of ideas and material to research, so I'm hoping onwe of you kind people may have some advice please.

Attached is a copy of the schematic, and the PCB layout. Drain resistors, L1 and L2, which are actually ferrite beads, and the Zobel are mounted on the copper side. T03's are mounted through a large lump pf copper.

The input cascode isn't implemented yet, input transistors are BC556/BC546, overload protection isn't fitted on the board and I've tried a variety of values for base stopper resistors. 3K9 seemed to work best to damp the oscillation, but it goes nuts when attached to anything a speaker and the moment the bias goes over 1.1 volts it starts oscillating like mad.

As far as I can tell it's stable apart from the parasitics, and it works fine in LTspice.
Answers on a postcard please!

[SpeakerScott]

Okay...two questions...

1. Are those really inductors in series with the gate of the MOSFETS?

2. Why is there a 100Ohm "isolation" resistor on the negative rail and no matching resistor on the positive rail?

In the ~30 seconds I spent looking at it those two jumped out at me as potential issues....

Scott.

[Elvee]

Hi Ian,

I find your idea interesting, but also extremely challenging: the combination of the highish impedance at the collectors of Q5/Q6 with the high capacitances of the MOS will create a strong local pole, which will make the global loop difficult to stabilize.
I'm not even sure the isolated composite will be stable when biased.
You'll have to devise a clever compensation scheme incorporating the output pole, so as to take advantage of it: no matter what you do, it will more or less remain dominant.
Or you could insert a bipolar follower between the drivers and the MOS, in order to simulate a bipolar CFP. Stabilization won't be an easy task either however.
Good luck.

PS
The ferrite beads in the gates have no effect at all: their impedance will always be much lower than the 2K2. You could use them alone if you choose to try my second proposition.

[Eva]

At which frequencies is your circuit oscillating? Conventional class-AB PCB layout style (like yours) is only good up to 1Mhz or so. If your output stage exhibits somewhat higher bandwidth, you have to resort to SMPS and class-D PCB design techniques.

Also, I don't see a RC network to simulate a resistive load at RF in your schematic, and supply decoupling is laid out in the worst way.

Even the inductance of the 0.22 resistors is a problem above 1Mhz, it will add to layout and supply inductances and it will resonate with MOSFET internal capacitances.

[ian_elvar]

Hi Scott

L1 and 2 are ferrite beads. I dug up an article on their use to prevent parasitics, so I thought I'd give it a go.

The isolation resistor should have a 1000uF filter cap by it, but it's missing in the schematic! It's definately on the PCB.

Elvee

Thanks, that would seem to make sense! I used some OP design elements from the ESP project here: http://www.sound.westhost.com/project27.htm and he seems to have ended up with a stable amp, albeit with different OP devices.

Eva

I'll let you know in a minute about the oscillation frequency. The schematic is from the PCB design software rather than spice, which is why it doesn't include a load circuit. For some reason I've pulled up a version which doesn't include filtering components shown. Sorry about that.
How could the supply filtering be improved? I assume you mean layout on the PCB?

Thanks for your comments so far

Ian

[AndrewT]

Hi,
what are the currents through the various stages?
VAS & Driver currents look like they are quite low.

Are Q5, 6 & 7 on a common heatsink/spreader?

R26 & 27 should be attached with a very cropped lead directly to the gate pins. Swap the locations of the resistors and inductors.
Omit the inductors? Do they need to be 2k2? What about much lower values?

Is C1 (150pF) returned to the correct node?

Temporarily swap a 2k pot for R2 to find best value for the fixed resistor.

Temporarily remove R32, 33, D5 & 6 (edit - not fitted yet)

C9 seems to be in an odd place. Vcc to Q11 base?

Do Buz have diodes to absorb inductive spikes if the protection triggers?

[ian_elvar]

Hi Andrew

I've got pots so I can adjust LTP and VAS current. At the moment they're set at around 4 and 6mA respectively, but neither seem to have any impact on the oscillation if I adjust them. Q5,6,7 are sandwiched together, with Q7's legs in the three square pads to the right of R18.

I haven't tried swapping the beads with the gate stoppers, but I'll give it a go. 2K2 is the lowest I can get without immediate oscillation when it fires up.

At the moment, R2 is 680, as I tried to see what would happen when I changed it. I'll see what I can do with a pot. R3 is 220 at the moment - I wanted to see what would happen if I moved the CL gain closer to the OL gain, but it made no difference to stability.

C9 is as per D Self - APADH P.230, to bring the slew rate back to symetrical if it suffers from cap. feedthrough on Q11 C-B. It's not currently fitted in the circuit - pads are just there for if I need them

C1 is returned to that point as per APADH P.248 Although it should be said that Self adds the cascode for a different reason to me - a potential helper for PSRR by holding the LTP pair at a steady VCE - whereas I was thinking about using it to up the rails a bit and not go over the low VCE of the LTP pair (40V). As it happens, it doesn't work, so the cascode transistors are replaced by links E-C.

Buz do indeed have internal protection diodes.

Cheers

Ian

[AndrewT]

Hi,
the idea for placing the gate resistors right at the gates is to minimise the lead inductance between the damping resistor and the gate capacitance. Your existing layout does the exact opposite. Maybe even crop the gate lead and crop the resistor lead and solder the two together directly below the heatsink flange.

[ian_elvar]

Yes, I see your point. I'll modify and let you know.

[AndrewT]

and what's the voltage across r22 r23? about 1100mV?
indicating just 2mA through the driver stage?

I would be tempted to increase the driver current to between 5mA and 15mA.

What about adding Source to power ground to Source decoupling?