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Old 5th June 2008, 05:21 PM   #1
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Default Classic op-amp schematic

I am cleaning my office and found my stash of "ancient" reverse engineering projects. This is the BB3554, it was near the top in its day ~1979. These product are now obsolete and there is no longer any IP interest. I thought some of you might enjoy seeing where folks were back then, in some cases not too far off from were things are now. This was in a BIG 12 pin TO-3 can (note the BeO substrate).
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Old 5th June 2008, 05:38 PM   #2
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Was this a hybrid circuit?

se
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Old 5th June 2008, 05:44 PM   #3
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Quote:
Originally posted by Steve Eddy
Was this a hybrid circuit?

se
Big hybrid discrete. I have some scary ones with comp caps all over.
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Old 5th June 2008, 06:19 PM   #4
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Wow!!!!

I used the BB3554 in 1982, for squirell-cage 63kA shunt active compensation. I got 2MHz bandwidth from that combo. The shunt used for development of SF6 HV circuit breakers, measurements of post-arc currents after zero (interruption).

I still have documentation and scientific report.
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Old 5th June 2008, 06:29 PM   #5
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No kidding, here it is:

(P.S.: If I was to write my professional memories, it would be probably more juicy than those of John ... )
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Old 5th June 2008, 06:38 PM   #6
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The shunt. In the deep dark times of iron curtain, I used Tek556 and Tek7844 dual beam scopes here.
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Old 5th June 2008, 08:37 PM   #7
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Further "classiscs"
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Old 5th June 2008, 09:23 PM   #8
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Default Bootstrapped jfet input cascode on BB3554

Hello,

Thanks for posting the schematic Scott. I was actually looking of using a jfet input cascode that is bootstrapped for a amp circuit like this chip.

I think that Q3 and Q4 cascode jfets must have higher Idss than the input Jfets Q1 and Q2 and higher Vp. This is going by some other jfet self biasing circuits I have seen though I don't know about other pre requisites.

Just out of interest does anyone have any references or experience with this arrangement ?

Thanks
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Old 5th June 2008, 11:12 PM   #9
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Default Re: Bootstrapped jfet input cascode on BB3554

Quote:
Originally posted by Fanuc
Hello,

Thanks for posting the schematic Scott. I was actually looking of using a jfet input cascode that is bootstrapped for a amp circuit like this chip.

I think that Q3 and Q4 cascode jfets must have higher Idss than the input Jfets Q1 and Q2 and higher Vp. This is going by some other jfet self biasing circuits I have seen though I don't know about other pre requisites.

Just out of interest does anyone have any references or experience with this arrangement ?

Thanks
The data sheets should be available on line somewhere. I think the FET second stage take off is key (for almost infinite current gain). Virtually no one has done this in IC's, probably for headroom issues.

Tomorrow I will post the most horrifying schematic I found.
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Old 6th June 2008, 06:22 AM   #10
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Datasheet is easily found by google, the Maxim part.
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