Output transistor power dissipation.
Does anyone know what the function is for power dissipation in an output transistor for a sine wave input ?
1/ The output transistor is only on for half of the sine waveform. 2/ As the output voltage approaches zero and V+ the pwoer dissipation approaches zero. 3/ Max power dissipation seems to be a maximum at half V+/ 
According to the National Semiconductor Audio/Radio Handbook, max Pd occurs when the peaktopeak output voltage is 0.637 times the power supply voltage. At that level, assuming that all Class B power is dissipated by the output transistors, dissipation is:
max Pd = Vs²/(2pi²Rl) = ~ Vs²/(20Rl) Vs= Supply voltage (absolute value of V+ and V added if using split supplies) Rl=Load impedance The end result of the calculation is the maximum total power dissipated by that amplifier channel. 
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Many thanks. My current method was to keep adding output pairs until they dont run too hot ! 
i once saw an AES paper that used 7075% rated output power as the figure for max dissipation (it's probably 70.7% since that's the RMS value of the waveform peaks at half the supply voltages).

No, maximum disappation is, as I posted above, when the PP output is 0.637 times Vs. No guessing to it.
NS provides the derivation for this figure in the book. I'm too rusty with my calculus to follow, but if anyone insists I can scan the page. 
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It would be interesting to see the page. 
You should have a look at this thread, as AndrewT made some very valid points regarding voltage and current phase shift, which for all loudspeaker loads will have a significant impact on device dissipation.
http://www.diyaudio.com/forums/showt...hreadid=106007 
The instantaneous device Pd is higher than the maximum Pd predicted by the equation in the handbook, Pd = Vcc^2/(2pi^2Rload). This equation gives the maximum AMPLIFIER power dissipation for a Class AB amplifier. It is the 50% efficiency point if you plot the curve of Pd vs Pout. I have done this many times and the point is accurately predicted. The problem is that this is the average power dissipation for the entire output stage. As noted, one half is doing on side of the sine wave. So the peak instantaneous is actually higher. Then you add in the phase difference between V and I and it goes up more. I don't know what the best number is to use for safe amplifier design. I think you can take into account the time at these higher levels, like FETs have a DC rating as well as a 10ms or some other short time SOA rating. Someday I'll figure it all out mathematically (all it is is math) and nail it down.
SL 
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Max Pd = 4Po(Max)/(pi²cosč) (Edit: the symbol for theta doesn't seem to be working...the last part of the denominator is cosine theta). Anyway, here is the proof for the previous formula (good for only a few days and something like 100 downloads, unless someone has a few MB of online space and would like to host it): http://download.yousendit.com/D87BE2D430B33F1A 
the number of output transistor pairs in your output is determined by your LOAD...
then your wallet....:D 
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