Hi Guys,
i started my tests with Borbely super buffer topology. But i modified the OLG because i thing that 40dB of feedback is too high and drop to 15dB. I checked hte FFT with my cd player with cd test at 1Khz to 0dB because i don't have a good sine wave generator and he has 0.0068% THD. I have cheap PS with regulator 7812 and 7912. The output for my all test is 2V rms. Any comments is welcome. Thank You! Maxpou
i started my tests with Borbely super buffer topology. But i modified the OLG because i thing that 40dB of feedback is too high and drop to 15dB. I checked hte FFT with my cd player with cd test at 1Khz to 0dB because i don't have a good sine wave generator and he has 0.0068% THD. I have cheap PS with regulator 7812 and 7912. The output for my all test is 2V rms. Any comments is welcome. Thank You! Maxpou
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Hi Peufeu,
because in my experience, i have a better sound when i reduce OLG in my cd player, line stage, power amp and i listen a old audioresearch 100.2 ( 6 dB of feedback) in my friend home and i loved the sound. I listened the Ayre audio system too and my jaw fell to the ground. So because I find it difficult to build a pre-amp without feedback I want to reduce as much as possible. thank you! Maxpou
because in my experience, i have a better sound when i reduce OLG in my cd player, line stage, power amp and i listen a old audioresearch 100.2 ( 6 dB of feedback) in my friend home and i loved the sound. I listened the Ayre audio system too and my jaw fell to the ground. So because I find it difficult to build a pre-amp without feedback I want to reduce as much as possible. thank you! Maxpou
. i tried to decrease OLG with local feedback but it does not work. How do i succeed?
Hi maxpou,
What I would try is to lose VAS loading with 47k resistor and try two 100k resistors each connected from drain of lower J-fet to gate of upper J-fet (referring to positive side of VAS), same thing for negative side.
I wander why you chose to exclude output stage from global negative feedback...if you enclose output stage in feedback loop your THD numbers will definitely go down big time, output DC drift will be better control, output impedance will go down and so fort.
What I would try is to lose VAS loading with 47k resistor and try two 100k resistors each connected from drain of lower J-fet to gate of upper J-fet (referring to positive side of VAS), same thing for negative side.
I wander why you chose to exclude output stage from global negative feedback...if you enclose output stage in feedback loop your THD numbers will definitely go down big time, output DC drift will be better control, output impedance will go down and so fort.
Hi maxpou,
If you are using it as a line amp, I would recommend you to lower your gain, so try to replace 220R resistor in FDB divider for one of 560R. Also, put something like 5~15pF(mica or polystyrene in parallel with 100k local feedback resistor). Next thing I would like you to try, if you can, is to replace 4V7 zeners for LM336-5V and replace 10k current sink resistor for J-fet CCS (use 2SK246 or BF256A/B/C with current program resistor in source)
If you are using it as a line amp, I would recommend you to lower your gain, so try to replace 220R resistor in FDB divider for one of 560R. Also, put something like 5~15pF(mica or polystyrene in parallel with 100k local feedback resistor). Next thing I would like you to try, if you can, is to replace 4V7 zeners for LM336-5V and replace 10k current sink resistor for J-fet CCS (use 2SK246 or BF256A/B/C with current program resistor in source)
Comments about the schematics :
- There are some dots (junction) missing, careful if you use Eagle for layout...
- I tried a similar circuit some years ago (but with JFET input and the rest bipolar) and didn't really like the sound
- Don't forget to plot OL gain and phase to check for stability
- About the last one : if you don't include the output stage in the feedback you will get some DC offset at the output, also it is not clear if the output JFETs work in source follower or current source
Don't forget to report how it sounds, though
- There are some dots (junction) missing, careful if you use Eagle for layout...
- I tried a similar circuit some years ago (but with JFET input and the rest bipolar) and didn't really like the sound
- Don't forget to plot OL gain and phase to check for stability
- About the last one : if you don't include the output stage in the feedback you will get some DC offset at the output, also it is not clear if the output JFETs work in source follower or current source
Don't forget to report how it sounds, though
peufeu said:
Hi Peufeu,
- Sorry for forget junctions, i corrected my errors
- If you don't like the sound, maybe you have other schematic at propose to me or mods.
- How can i check the phase?
- I check my output DC with and without the output stage in feedback and i don't have the problem my DC is stable
- My output jfet work in source follower at Idss bias.
Thank you! Maxpou
To check for stability you would plot the open loop gain's phase and magnitude.
You can do that with the loop open (you will need to set a precise DC offset in Spice to zero the output and send a small signal at the input).
Then you close the loop, and you can plot it again by dividing the output voltage by the error voltage at the input. This gves you the open loop gain.
But your design is a current-feedback amplifier, so how to apply this is slightly trickier.
A simpler thing to do is to plot V(out) from DC to say, 100 MHz, and look for indications of ringing or bad damping. Try simulating it with a bit of capacitance at the output, too, like the capacitance of the cable you will use.
You can do that with the loop open (you will need to set a precise DC offset in Spice to zero the output and send a small signal at the input).
Then you close the loop, and you can plot it again by dividing the output voltage by the error voltage at the input. This gves you the open loop gain.
But your design is a current-feedback amplifier, so how to apply this is slightly trickier.
A simpler thing to do is to plot V(out) from DC to say, 100 MHz, and look for indications of ringing or bad damping. Try simulating it with a bit of capacitance at the output, too, like the capacitance of the cable you will use.
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