Cascode Output Stages

[Lumba Ogir]

Peter,
select R17 for the desired current.

[pietjers]

Hi Lumba,

Thank you!

Could you please comment (or someone else) on the DC offset issue?

Peter

[AndrewT]

Hi,
I have bf244a and bf244b and bf245c.
Can I use the 245c as t15(upper) and the 244b or 244a as t16(lower) in the CCS?

[Lumba Ogir]

Andrew,
yes. Go for the lowest Idss group providing the current you need with some value of source resistor.

[pietjers]

Why would one use a mix of BF244 and BF245 devices? They are very much the same.

Be aware: the pinout is NOT the same!

http://www.farnell.com/datasheets/42147.pdf

Peter

[Lumba Ogir]

Peter,

Why would one use a mix of BF244 and BF245 devices? They are very much the same.

You don`t have to, can just use BF244. They are not the same. Are you going to order?

[KSTR]

To the best of my knowledge, BF244 and BF245 are the same silicon, only different pinout.

I've used BF245C's to cascode BF245A's which works great for ~0.5...1.5mA CCS... still you need a source resistor for a clearly defined current. The A at ~1mA was choosen for mimimum tempco and low voltage drop, and the C for max cascode voltage.

- Klaus

[ppl]

Hello, If you are using a cascoded J-FET current source the Idss of the Upper fet should be slightly greater than the Lower fet so as to properly Bias the Lower fet. In addition this TI app note on Pg.11 shown is jfet casscode http://focus.ti.com/apps/docs/techdo...ctName=sboa046

Also this EDN article is a very good read on the subject. http://www.edn.com/article/CA6330095.html

I have used this type of current source a lot and they work great and can give isolation greater than 120 dB if enough voltage drop is available to properly Bias the FET’s . You may have noticed that this type is also used in my Cascoded output stage (Post#51)

While these work great I am considering moving over to a Cascoded BJT Current source as the Jfets current change quite a lot with tempo and this causes DC offset to be > than it should be. I am employing these types of J-FET current sources thought the Amplifier this output stage is used. The Problematic current source is the one for the LTP as these changes most greatly influences the DC offset. In my application of the Cascoded output stage referenced to in post#51 the feedback includes the Output stage at the moment, however due the low output impedance of this Cascoded output stage I am going to try operating it outside the LOOP.

Peter!
The DC offset issue you are having is best solved using complementary current mirrors with a common Bias current generator. Attached is a Stand alone version of my cascoded output stage intended to be used as a Unity gain Line/Headphone Driver. Provisions are included for DC offset adjustment you could upscale this paying attention to jfet voltage limitations (Again another reason I am considering going the Cascoded BJT way.

[CBS240]

Hi

Here is a good application note on CCS. This paper part 1 and part 2 by Mr. Borbely is a must read if you like
J-fets. Basically you want the cascade transistor to have a larger Vgs so that the source transistor Vds is greater than Vgs or the source fet will not operate in the saturation region. The choice is whether it is more economic to use a single fet CCS and whether it is worth it for the reduction of output conductance to cascade. As for Id variation w/temperature, refer to the transfer characteristics and choose Id at the zero temp coefficient Q-point. There is a special place in my heart for J-fets. They can be very useful.

[pietjers]

Thank you all for the very valuable contributions!! Also very interesting articles you have mentioned. A lot of reading to be done I’m afraid…..

Klaus and Philip, nice to see you back here!


This is what I tried yesterday. Instead of the FET CCS which bias the LM4041/TL431, I used a fixed resistor for simplicity. DC drift is the best of all complementary CCS I have tried so far. The strong point is that these LM4041 and TL431 CCS have feedback and low TC.

I tried a common CCS with current mirrors, but that was not good enough to give the desired DC stability. Did however not try the double mirrors. When you catch one of the mirror transistors with your fingers, DC at the output immediately starts drifting away.

To have two CCS in series is like two Constant Voltage Sources in parallel, always problematic.

Peter