Leach150 phase margin problem!!!

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Hello Everybody!!
I have a problem of Leach 150
I have make a Leach150 power AMP and it is working fine, but in spice simulation
some problem confuse me very much!!
It is phase margin problem!!
I use Spice to simulate the Gain and Phase,
but I found the phase margin is not enough!, it almost 0 degree.
I simulate in transient it is very normal,
and the transient testing result use function generator that still no problem,
could I ignore the phase margin??, but in the text book, the PM at least is 35 drgree
or I am really too stupi that I simulate wrong??

please help me, thank you very much
have a nice day!!

my.php




The phase margin image is here!!

http://img528.imageshack.us/my.php?image=leachpmproblemov3.jpg

I almost crazy, don't know what is wrong!!!
 
I am not familiar with your amp's circuit. But to find the phase margin, to judge the stability of a feedback system, you have to do it with the OPEN-loop gain and phase.

There are also ways to do it with the loop closed, such as the Tian method. You can look in the Files section of the LT-SPICE users' group, at http://tech.groups.yahoo.com/group/LTspice . There is a file you can download that gives the locations of all of the files. Then look for files called Loopgain3.asc and Loopgain2.asc . I use the second schematic in Loopgain3.asc . You can download Ltspice (aka SwitcherCad), to view the files, and then adapt them to whatever Spice you are using. LTspice can be downloaded here: http://ltspice.linear.com/software/swcadiii.exe .

Or, with "the simple method", you can insert an AC source just before a high-impedance input, such as the summing node for your feedback, with the source's + output toward the high-impedance node. If the AC source's + side is labeled In and the - side is labeled Out, then you can plot V(Out)/V(In). If the high-impedance node is really high-impedance, such as an opamp input, then the simple AC source method should be accurate-enough up to tens of MHz.
 
Hello Tom
Thanks your information
I give the AC signal in before the input filter,
this is AC in
and output I measure 2 point,
one is 3rd stage output (power AMP output)

another is 2nd stage output (voltage AMP output)

those result are almost the same,
this confuse me a lot

I also do the open-loop simulation, but the result is more bad
the phase reach -2xx degree

does leach150 itself have low phase margin naturally???

thanks a lot !!!

have a nice day!!!
 
Hello My Lord!!

I upload some PIC in the imageshack, because my first post some pic cannot see

Pic1: it is my schematic, it was a little modify from original Leach150
the source is one Chinese audio DIY site http://www.diyzone.net/index.php

http://img134.imageshack.us/my.php?image=dzleachmm1.jpg

Pic2: it is my spice schematic

http://img182.imageshack.us/my.php?image=leachspicemd9.jpg

Gain and Phase simluation result

http://img518.imageshack.us/my.php?image=gainphasesimsb7.jpg

It is so stranger, please help me!! thanks very much!!
 
mclarenpingu said:
Hello Tom
Thanks your information
I give the AC signal in before the input filter,
this is AC in
and output I measure 2 point,
one is 3rd stage output (power AMP output)


I think you should input AFTER the input filter. The input filter will cause a phase change related to its cutoff frequency, which is much lower than the amplifier bandwidth, per se, and is outside the feedback loop.
 
mclarenpingu said:
Hello Tom
Thanks your information
I give the AC signal in before the input filter,
this is AC in
and output I measure 2 point,
one is 3rd stage output (power AMP output)

another is 2nd stage output (voltage AMP output)

those result are almost the same,
this confuse me a lot

I also do the open-loop simulation, but the result is more bad
the phase reach -2xx degree

does leach150 itself have low phase margin naturally???

thanks a lot !!!

have a nice day!!!

Using your normal input point, before the input filter, with the system running closed-loop, will _NOT_ work, for phase-margin stability analysis. No way. Don't bother. You're totally wasting your time. (Is that clear-enough?! :)

Perhaps you could post the spice schematic for your open-loop analysis, and the resulting gain and phase plot. THEN maybe someone can help you.
 
I just remembered that I already posted an example of the Tian method, with LTspice, here:

http://www.diyaudio.com/forums/showthread.php?s=&postid=1298611&highlight=#post1298611

That post does not include any stability results, but DOES include a JPEG of the circuit schematic, showing the Tian stability "probe" inserted into the closed-loop system (AND a downloadable ZIP file containing the LTspice simulation files).

In case you don't want to download LTspice, you can just look at that schematic, make your own, and get the details correct by copying and pasting into your spice schematic, from the following:

If you insert a series AC voltage source, named

Vi

as shown in the schematic, with AC amplitude

{u(-prb)}

and, after that, an AC current source from ground, named

li

(i.e. L and I), with AC amplitude

{u(prb)}

and label the node where they join with the name

x

and run an AC Analysis and step the prb parameter from -1 to 1, with the spice directive:

.step param prb list -1 1 ; set prb=0 to turn off probe

using the AC Analysis directive:

.ac dec 30 .001 10Meg

then you can plot the open-loop gain and phase by plotting the following expression:

1/(1-1/(2*(I(Vi)@1*V(x)@2-V(x)@1*I(Vi)@2)+V(x)@1+I(Vi)@2))

I always grounded the signal-input node, when running the above for stability analysis.
 
Hello gootee
Thanks your great help
I think I might be wrong and I see the Phase margin to the dB axis
because I am simulate in midnight.....feel so tired............
sorry

Today I do some simulate I feel input filter seem no the root cause
I will follow you instruction and so the simulation
and I will post the result ASAP

thanks a lot!!!!!
 
Hello All
I have some problem about the gain/phase
original, I use this schematic to simulate

http://img207.imageshack.us/my.php?image=guopsimnb5.jpg

but it compare with LTspice example, it is wrong.......
and later I think, my original schematic, it should call "frequency response"
in Smith text book, it be used to test one MOSFET, BJT or OPAMP,
but if I use this simulation method to simulate gain/phase, does it is wrong???
or it just can simulate open-loop system??

But in gain/phase bode plot, it usually show v(out)/v(in), like a transfer-function
so I feel like gain/phase can be expressed by v(out)/v(in)
Am I wrong totally??
Please Genuis Lord teach me!!!

thanks very much, that will be a great help for me!!!
 
Hello All
Sorry bother everybody many time
I think I want to simulate this figure.
(It is copy from TI OPA378 datasheet)

http://img509.imageshack.us/my.php?image=opa378tiok0.jpg

it is called open loop gain
I regard this is gain/phase and stability simulation for a long time,
but don't know right or wrong....

Does class AB audio AMP need this simulation??

Again, I regard Class AB very simliar with OPAMP, AudioAMP might = OPAMP+ output buffer.....
but don't know right or wrong....

but it seem to the difference between open-loop gain and close-loop gain...........

thanks very much!!!
 
Your schematic from Post #12 could be used for CLOSED-LOOP frequency-response gain and phase plot.

But that schematic can NOT be used, when configured as you have shown it, for the OPEN-LOOP gain and phase plot, for determining phase margin, for stability analysis. It simply will not work, for phase margin, if configured that way. It's completely different.

To get a plot that could show the phase margin, you would either have to a) break the loop and insert an AC source (just before the opamp's feedback input, with V(in) defined as opamp's feedback input (i.e. one side of inserted AC source) and V(out) defined as the other side of the AC source that you inserted), OR, b) use the Tian "probe" method that I have already mentioned.

Maybe you should do some google.com searches for "control system OR feedback loop stability OR phase margin", or, "opamp OR amplifier phase margin" (without the quotes).
 
Below is a schematic that will work, in LTspice, for stability analysis.

An externally hosted image should be here but it was not working when we last tested it.


You will have to enter the "AC Analysis" parameters, either the first time you try to run it, or, by selecting Simulation --> Edit Simulation Command from the schematic menu. I used the "Decade" type plot, with 200 points per decade, and Start Frequency .01 and Stop Frequency 1000Meg.

After running it, right-click on a plot label and enter v(out)/v(in), to make it plot the gain and phase of v(out)/v(in).

Then, look for the point where the gain passes downward through 0 dB (i.e. where gain goes below 1), and look at the phase angle at that frequency. That will be the phase margin.

Measuring the plot (shown below) from the schematic above gives a phase margin of about 33.6 degrees.

An externally hosted image should be here but it was not working when we last tested it.
 
Hi apparatusonitus,

Thanks for posting your Tian Method results.

It looks technically stable, since the gain goes below 1 (0 dB) before it inverts (i.e. before phase goes to -180 or 180), avoiding an overt "positive feedback" condition [which is basically what phase margin stability analyisis is all about]. (And I _think_ that since your phase angle starts at 0 deg, instead of 180, maybe you can add 180 deg to the apparent phase margin, giving 67 degrees.)

I might tend to be a little more concerned about the area between 500 kHz and 1 MHz, where the phase angle gets to within about 25 degrees of inverting, while the gain is still up around 40 dB.

It might be wise to try banging it hard with some almost-square waves, in the time domain, to see what kinds of ringing you can incite.

However, the original AD797 chip is well known for being close to unstable, under some conditions. So that might actually lend some credence to your version's faithfulness to the original. :)
 
gootee said:

It looks technically stable, since the gain goes below 1 (0 dB) before it inverts (i.e. before phase goes to -180 or 180), avoiding an overt "positive feedback" condition [which is basically what phase margin stability analyisis is all about]. (And I _think_ that since your phase angle starts at 0 deg, instead of 180, maybe you can add 180 deg to the apparent phase margin, giving 67 degrees.)

Thank you for replay gootee, especially for explanation how to do phase margin analysis...I wasn't even aware about examples in educational file at SwCAD ;-)

gootee said:
I might tend to be a little more concerned about the area between 500 kHz and 1 MHz, where the phase angle gets to within about 25 degrees of inverting, while the gain is still up around 40 dB.

It might be wise to try banging it hard with some almost-square waves, in the time domain, to see what kinds of ringing you can incite.

I've already done that with square waves at 1, 10 and 100kHz in open/closed loop and 600R output load...everything seems OK as far as I can see (as a non EE, that is)...Should I torture it some more with reactive load, like 1-100nF in parallel and inductance in series (how much?) with 600R resistive load?

gootee said:
However, the original AD797 chip is well known for being close to unstable, under some conditions. So that might actually lend some credence to your version's faithfulness to the original. :)

I've followed the original design as much as possible according to my needs, availability of components and layout (opamp is in SMT)...changes are in areas like voltage references (LEDs) and current sources (again based on LEDs), active loading for folded cascade transistors and output buffer (triple EF in class A)...As far as I can tell, this is the best discrete opamp design with impeccable results simulation wise...two thumbs up for Scott Wurcer!
 
aparatusonitus said:


Thank you for reply gootee, especially for explanation how to do phase margin analysis...I wasn't even aware about examples in educational file at SwCAD ;-)

I've already done that with square waves at 1, 10 and 100kHz in open/closed loop and 600R output load...everything seems OK as far as I can see (as a non EE, that is)...Should I torture it some more with reactive load, like 1-100nF in parallel and inductance in series (how much?) with 600R resistive load?

I've followed the original design as much as possible according to my needs, availability of components and layout (opamp is in SMT)...changes are in areas like voltage references (LEDs) and current sources (again based on LEDs), active loading for folded cascade transistors and output buffer (triple EF in class A)...As far as I can tell, this is the best discrete opamp design with impeccable results simulation wise...two thumbs up for Scott Wurcer!

You're welcome. But I don't consider myself an expert at this stuff, anymore (maybe two or three decades ago, I wasn't bad). So I hope that someone else will chime in, to verify (or question) the conclusions et al.

Congratulations on your discrete AD797. And yes! Scott Wurcer! I greatly admire him, too. He's one of those rare guys whom I wish lived next door to me. :)

With the square waves, remember that the edge-times are what matters, more than the repetition rate ("frequency"). And yes, I would _definitely_ try it with capacitive loads. But be mentally prepared for some "ugliness", at first (just in case :) . Note that you will probably want to make sure that you have an RF lowpass filter on the input, and/or that you limit the input square wave's edge times to something reasonable (versus the amp's max slew rate and the output amplitude). Otherwise, things can look much worse than they might ever really get.

Note, too, that sometimes, even if an amp can drive 1 uF or 2.2 uF OK, and can also drive .001 uF OK, it still might oscillate with a 0.1 uF load (just for example). At any rate, you will probably want to be able to drive a load at the other end of some length of cable (or PCB trace, at the least). And cables (and PCB traces) always have some capacitance. You can look up some common cable capacitances (usually expressed "per foot"), and can probably model them as small capacitors in parallel with your resistive load. At least a few hundred pF or more is probably a reasonable minimum.

I think there is actually a sort-of "standard" for acceptable ringing into a 2.2 uF purely-capacitive (I think) load, for audio amplifiers. I saw it on the web, somewhere, within the last year or so, IIRC. There was something about the percent max overshoot, and something about it dying out within 5 (??) cycles, to within a certain percentage of the initial overshoot. But that's also all assuming a complete amplifier. And a lot would depend on things like the Thiele network (the parallel L and R that that are usually in series with the output, plus the Zobel network(s)). And maybe there would be an R in the forward path, after the amp, but inside the feedback loop, possibly with an L in parallel with the R, which is one way to condition an amp to deal with capacitive loads, IIRC.

[Aside:] Also, it sometimes turns out that you can design an amp that will basically never have any overshoot, as long as you have enough excess current-drive capability (that's also fast-enough), and the right kind of configurations for everything else. I designed some like that (only simulated, so far), not too long ago. But they were all "composite" amps, IIRC, i.e. with a chipamp inside the feedback loop of a fast opamp. One of the sort-of "easy" ways that I found, to make an amp that can drive large-C loads, was to design the amp such that it HAD to have some relatively-large minimum capacitive load, just to be stable. You definitely need some excess current-drive capability (think "several paralleled chipamps"), for the way I did those. But they could drive nearly their maximum ouput amplitudes into 10 uF with no overshoot, while using their max slew rates almost right up to the corners of the squarewaves. It seemed kind of cool, at the time. The square-wave response was really gorgeous! :) And the THD @ 20 kHz simulated at about .0001%, even using TI.com's OPA541 (E-version) spice model for the chipamps.
 
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