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Old 6th November 2007, 11:09 AM   #1
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Default Finnish-Zenish fet amp

Hi everybody,

I hope this post 1) goes to the right place 2) is interesting

Attached is a schematic (from a simulation software) for an amplifier I built from parts that happened to be in my shelf at the time. It surely was inspired by Zen number five. I just put a j-fet stage in front of the basic common source thing and arranged the feedback to 3 different places. The amp is built into a polished brass casing. Unfortunately I don't have a picture. Works well as a mirror too.
I had a moment of great joy when a realized how neatly the two stages play together. Input impedance is really easy. The second stage fet's don't cause high freq nonlinearities, because of the driver stage. Nothing special of course. But then it was nice to notice, that the topology makes power supply regulation (or heavy filtering) unnecessary. I do have CRC-filtering with huge caps, but nothing else. It's also nice to get rid of signal caps. J-fets work well as the first stage, because they are so conveniently self biased. The right drain current value for zero tempco has to be chosen, but after that the amp is very stable in idle currents. There is room for very different feedback tastes. I chose the "golden" middle path between "right" and "versatile"
Due to the total amount of different feedbacks the amp is highly linear for the first 10 Watts. (3rd harmonic @ -75dB for the best MOSFETs)

The performance without negative feedback is quite similar to NNF triode amps, but with higher percentage of high harmonics above 15 watts or so.

I used K170 and J74, and the venerable IRFP240 and -9240.

If you are avare of highly similar topologies (no BJT's) tell me.
I mainly spend my limited forum time in Prodigy DIY, which is for pro audio stuff. (my profession)

If you have interest in the project and schema I can write a bit more and provide a version with the current and voltage values. Now I have to stop.

I posted the schema with description to Mr Pass, and he asked me to post it here too.

BTW: The sound is good.

-Jonte
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File Type: pdf j-fet_amp.pdf (13.7 KB, 527 views)
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Old 6th November 2007, 02:39 PM   #2
dimitri is offline dimitri  United States
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Quote:
If you are avare of highly similar topologies (no BJT's) tell me.
http://www.wimdehaan.nl/variousamps/mjamp/index.html

I'll try to find the same four fets amp in one of the Japanese magazines. Output MOSFETS were different and no 2nd harmonic pot.
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Old 6th November 2007, 05:04 PM   #3
Nrik is offline Nrik  Denmark
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Neat.
Yes we would like to see some more.
What idle current is it running at?
for how high supply voltage have you testet it?
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Old 6th November 2007, 08:37 PM   #4
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This is just simulated....?
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Old 7th November 2007, 04:12 AM   #5
fab is offline fab  Canada
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Default Re: Finnish-Zenish fet amp

Quote:
Originally posted by Jonte Knif
.... If you are avare of highly similar topologies (no BJT's) tell me. ..
.

Have you searched the forum at http://www.diyaudio.com/forums/showt...456#post692456 ?
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Old 7th November 2007, 09:58 AM   #6
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Like I wrote the amp has been built and measured in real life too. And listened too. And used as a mirror...

I actually made my amps with dual mosfets at the output, because I have 4 Ohm speakers.

I used 800mA per device. This was about the maximum the heatsinks could dissipate. They run at 55 degrees.

So far the schemas posted here are quite similar but I have a few comments about the differences.

One of the schematics had source resistors on the j-fets. Not good if you like thermal stability. I tried. It causes nice thermal feedback. When the amplifier warms up, the j-fets drain current raises, which then raises the mosfet current.
The process is slow, but unavoidable.
High transconductance j-fets have their zero tempo at max current. Therefore source resistors are not recommended. For my topology I chose a pair with 10 mA Idss, but it is not that important.

The 2D-trim is fairly effective, but not obligatory. You have to first think it as a local feedback formed by two resistors to the gates of the MOSFETs. It plays an important role in the performance and philisophy. I didn't like the idea that the output stage is a pure transconductance amp, therefore I used both source and gate feedback to get the "triode-like" performance.
This is, in a way, similar to zen nro 5.

Global feedback is always more effective than local, so here we are again. Using local feedback has one definitively nice effect. The open loop miller capacitance goes down, and the wimpy j-fets are able to drive the mosfets with good linearity and speed. Therefore distortion does not increase much at high frequencies, which (I believe) is very important in any amp.

But, without local feedback the amp does measure better. For sure.

The phase lead capacitor in the feedback loop is not necessary. The amp is stable without it.

I used 22V rails. The reason is two-fold. J-fets don't take much more, but more importantly I was able to use 25V caps, and got nice amount of capacitance with modest amount of money. The CRC network is 47mF-0.47Ohms-47mF. This DOES leave some ripple, but not audible with normal speakers.

Class A output to 4 ohms was 35 watts.

Here I have a question:
This kind of topology makes it a bit difficult to define the class because the output stage works in class A to quite high levels if the definition is that the devices never go to "off" state. There is some current left even when approaching clipping. Therefore it seems that the amp puts more power in class A than the idle currents suggest.
What is your opinion about the matter? Any way, nice feature in deed.

-Jonte
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Old 18th November 2007, 02:27 AM   #7
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Quote:
Originally posted by Jonte Knif
High transconductance j-fets have their zero tempo at max current. Therefore source resistors are not recommended.
This is untrue.

Each FET will exhibit a zero tempco operating point. The channel resistance increases with temperature, while the Vgs threshold drops with temperature. When these effects balance, you will have a zero tempco point. Oxner has derived this in his books. Out of print, but still available on the internet.

For the K170/J74 pair, the zero tempco point is more like 18 mA. This is not obtainable with standard biasing techniques.
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Old 18th November 2007, 09:37 AM   #8
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Default Drift

Untrue, really? I'm confused.

I have two reasons to believe that it is at least not far from true.

The most important source was Borbely's article about jfets. It explains the same equation as your source, but the outcome is different.

http://www.borbelyaudio.com/adobe/ae599bor.pdf

According to him the zero tempco is close to Idss in high Gm j-fets like K170. Look at the curves in picture 3B . There are also the equations for calculating the zero tempco, and it is not at all close to 18mA with K170 and J74. It was the only source I had, and I think it is reliable. Because:

The second reason is experiment. When choosing K170/J74 j-fets (according to Idss), it is easy to notice that during the measurement, when the fet is warming up, the low Idss fets drift a lot, and the ones with Idss close to 12 mA don't. I believe my multimeter, and therefore I also believe Borbely's article. Still higher Idss, and the drift is negative. Confirmed in my measurements too. Very close to Borbely's curves.

I have not tried to find the absolute minimun drift, but my amp first had two paralled K170 and J74 with about 50 Ohms source resistors. I was thinking that "this will help to cancel the effect of drift etc." Well, it did not. Quite the contrary, of course. Dropping the source resistors and other pair of j-fets of the drift was _much_ smaller. To the extent that it was insignificant. Before it was a real problem. I wrote that the absolute Idss value is not important, but I take my words back. You should get close to 12 mA. Sorry for that.

Is there another way? My way worked, is in accordance with Borbely's article , and was simple to understand.

-Jonte
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Old 18th November 2007, 05:21 PM   #9
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Please re-read Borberly's article a few times. The information is mostly correct, but not presented in a useful way.

The key equation is Vgs = Vp + 0.63 V.

This is only true at on specific temperature. If you look at the Toshiba data sheet, you will see that this only occurs at room temperature with a 12 mA Idss part if the bias voltage is +0.13 volts. This requires an external bias supply. Or you could run it at 100 C, but that is not something I would recommend.

Or you could run a 16 mA Idss part at 25 C (sorry, my number of 18 mA was from memory and slightly off), to reach zero tempco. But there are two big problems here:

a) The highest Idss range to obtain is V, which ranges from 10 to 20 mA. That means that (statistically), over half of the parts you purchase won't be able to reach the zero tempco.

b) You have to run the part at 16 mA to be at zero tempco. If the part has a higher Idss than 16 mA, you can run a source resistor. In general, this is a very GOOD thing, as it will stabilize the operating point of the circuit, making it less sensitive to ambient temperature changes among other things.

c) Creating a design that only works with a small fraction of the available parts, requires extremely careful hand matching of parts and commensurate selection of each source resistor is not, in general, a very useful design.

Any way, if you read and understand Borbeley's article, you will see that your claim "High transconductance j-fets have their zero tempo at max current. Therefore source resistors are not recommended" is untrue. Instead, it is correct to say that any JFET will have their zero tempco when operated 0.63 V above their Vgs threshold voltage. These are NOT the same statement.
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Old 18th November 2007, 11:18 PM   #10
dimitri is offline dimitri  United States
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Quote:
it is correct to say that any JFET will have their zero tempco when operated 0.63 V above their Vgs threshold voltage
Charles, this is much more universal than specify Ids. I remember during Soviet times the JFETS had 3-4 V pinch-off voltage, and we set the Vgs 0.6V above this for thermostable point. The current was 0.5-1mA
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