well, it seems I'm on one of the rare cases where simulation is completely failing ... this post
http://www.diyaudio.com/forums/showthread.php?postid=1059404#post1059404
contains a very well circuit to test open loop gain and phase margin, but with a warning of this type
>>>>>>>>>>
Please keep in mind, however, that phase margin and gain margin are not perfectly reliable guides
and that there are many pathological cases in which they fail spectacularly,
even though for most commonly encountered systems, stability can be determined rather well by these measures
>>>>>>>>>>
In my amp with C2 in place I should gain additional 30° of phase margin but instead it oscillate at about 1Mhz
http://www.diyaudio.com/forums/showthread.php?postid=1059404#post1059404
contains a very well circuit to test open loop gain and phase margin, but with a warning of this type
>>>>>>>>>>
Please keep in mind, however, that phase margin and gain margin are not perfectly reliable guides
and that there are many pathological cases in which they fail spectacularly,
even though for most commonly encountered systems, stability can be determined rather well by these measures
>>>>>>>>>>
In my amp with C2 in place I should gain additional 30° of phase margin but instead it oscillate at about 1Mhz
C2 increases loop gain at high frequencies, that is the way it lowers the closed loop gain at high frequencies. Both plots look stable I think, but did you model the inductance of the leads of the output transistors? Try inserting inductance to simulate it's leads, maybe 10-100nH depending on length.
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