Hi fellows,
I have been designing my very first power amplifier, and now I've reached the point of pspice telling me this one is gonna work quite fine. But I would like to have comments whether there are some mistakes that pspice can't see.
I would also like to understand the following issues better:
-stability (yes, I know about reducing the gain below 0 before phase shift reaches 180 degrees, but when I simulate this one with 20kHz square wave, 1Vp-p at output, I still see some vibration in the waveform. Is it possible to get rid of it totally?)
-The meanings of caps C5, C7, C8, C9, C10 & C11. For now I've given them some more or less random values, and I have not seen their effect during simulations. If I had to guess, I would say that the caps C5, C7, C9 & C10 stabilize the currents during sudden changes in voltages (for example if the input signal raises or falls very quickly).
-also the purpose of R16, R18 & R19 is not clear to me.
-I can feed this amplifier with up to 2.5 Vp-p sine (1 kHz) until the output gets clipped, is this good or not? I get 40 Vp-p output.
Anyway, right now my bias currents are fine, thd seems to be acceptably low, offset is 30 uV, bandwidth and gain are also fine. So I'm only concerned about the stability now. I have tried raising the values of R7-R10, but after that I have to adjust the bias currents and offset which eventually leads me to the starting point. I mean that I see no changes in the 20kHz output square wave.
If you have something in mind, please share it!
If the pdf-file is not visible, it can be found here
p.s. I forgot to add that when I'm simulating the stability, I use 470nF or 47nf caps in parallel with the 8 ohm load.
I have been designing my very first power amplifier, and now I've reached the point of pspice telling me this one is gonna work quite fine. But I would like to have comments whether there are some mistakes that pspice can't see.
I would also like to understand the following issues better:
-stability (yes, I know about reducing the gain below 0 before phase shift reaches 180 degrees, but when I simulate this one with 20kHz square wave, 1Vp-p at output, I still see some vibration in the waveform. Is it possible to get rid of it totally?)
-The meanings of caps C5, C7, C8, C9, C10 & C11. For now I've given them some more or less random values, and I have not seen their effect during simulations. If I had to guess, I would say that the caps C5, C7, C9 & C10 stabilize the currents during sudden changes in voltages (for example if the input signal raises or falls very quickly).
-also the purpose of R16, R18 & R19 is not clear to me.
-I can feed this amplifier with up to 2.5 Vp-p sine (1 kHz) until the output gets clipped, is this good or not? I get 40 Vp-p output.
Anyway, right now my bias currents are fine, thd seems to be acceptably low, offset is 30 uV, bandwidth and gain are also fine. So I'm only concerned about the stability now. I have tried raising the values of R7-R10, but after that I have to adjust the bias currents and offset which eventually leads me to the starting point. I mean that I see no changes in the 20kHz output square wave.
If you have something in mind, please share it!
If the pdf-file is not visible, it can be found here
p.s. I forgot to add that when I'm simulating the stability, I use 470nF or 47nf caps in parallel with the 8 ohm load.
C5, C7: Wired like that these capacitors do practically nothing. These are supposed to couple the AC component of the supply rail(s) to the other "voltage reference” node of the current source; this to cancel AC current flow through the reference. You want steady DC current to control the CCS transistors' bases to get constant current. Since you practically just bypass the rail’s AC to flow through R16 you still have the same AC current flow in the reference. To prevent this you should, for example, split the R16 into four resistors, hook up their middlemost node to ground and connect the capacitors to the other interconnecting nodes.
Once you visualize how the configuration works you see that the same AC now affects at both ends of the current source’s reference. I'm pretty sure there are plenty of alternative methods to get the same result as well. I hope this explanation was clear enough. The capacitance values are ok.
C8: This capacitor bypasses the VBE multiplier. Thus VBE multiplier only affects on DC, like it should do. The value is maybe a bit high but it won’t do no harm.
C9, C10: Took a while to figure it out. Always draw the dots to mark connecting nodes! Anyway, The Zeners and R18, and R19 form the important DC voltage references for the cascade transistors’ bases. C9, C10 filter these references. Values are again ok.
C11: Bypasses R23. Some people say this capacitor enhances clipping recovery but I have never experienced it doing that. Some people also say it is not required in dual supply amps. Anyway, in my experience it has some minor effects to clipping behaviour of the output stage. Most of them are hidden by NFB anyway. Some one else might know a lot more about this that I do. Value seems too high.
Once you visualize how the configuration works you see that the same AC now affects at both ends of the current source’s reference. I'm pretty sure there are plenty of alternative methods to get the same result as well. I hope this explanation was clear enough. The capacitance values are ok.
C8: This capacitor bypasses the VBE multiplier. Thus VBE multiplier only affects on DC, like it should do. The value is maybe a bit high but it won’t do no harm.
C9, C10: Took a while to figure it out. Always draw the dots to mark connecting nodes! Anyway, The Zeners and R18, and R19 form the important DC voltage references for the cascade transistors’ bases. C9, C10 filter these references. Values are again ok.
C11: Bypasses R23. Some people say this capacitor enhances clipping recovery but I have never experienced it doing that. Some people also say it is not required in dual supply amps. Anyway, in my experience it has some minor effects to clipping behaviour of the output stage. Most of them are hidden by NFB anyway. Some one else might know a lot more about this that I do. Value seems too high.
Hi
C11 bypasses R23 in order to create an AC current path from the base of the NPN to the emitter of the PNP driver. This allows the PNP driver to suck the charge out of the NPN base in order to turn it off during the negative going cycle. If the NPN output doesn't turn off by the time the PNP begins to turn on, there will be too much cross conduction and the devices may fail. This can be noticed to a greater degree with higher frequencies in the 100's of Kilohertz range, as it requires more AC current to charge and discharge the input capacitance of the transistor at faster speeds. IMO, a couple of hundered uf cap across R26 wouldn't hurt either. Voltage for these caps can be small as they will not see a voltage greater than a few volts.
I agree with teemuk on how to fix C5 & 7.
It is important to have the CCS's and cascode references free from AC. Zeners are good for this, but do gererate some noise. However, imagine the rails have fluctuation from the PS filter or from the output current. The zeners, D11 & D12, will have steady 4.7V across them but the power supply ripple voltage will still be on R18 & R19, and thus the base of Q's 17 & 21. You want to eliminate this AC with respect to GND, not the rails. IMO, a self bias J-fet CCS, a resistor, and a small cap is a better reference because the voltage is dependent on a steady current, not just a zener voltage reference. But I suggest keeping it as is here for simplicity and understanding. Maybe change the placement of the zeners and R18/19 and use a 45V zener and like 3K for the resistors?
C11 bypasses R23 in order to create an AC current path from the base of the NPN to the emitter of the PNP driver. This allows the PNP driver to suck the charge out of the NPN base in order to turn it off during the negative going cycle. If the NPN output doesn't turn off by the time the PNP begins to turn on, there will be too much cross conduction and the devices may fail. This can be noticed to a greater degree with higher frequencies in the 100's of Kilohertz range, as it requires more AC current to charge and discharge the input capacitance of the transistor at faster speeds. IMO, a couple of hundered uf cap across R26 wouldn't hurt either. Voltage for these caps can be small as they will not see a voltage greater than a few volts.
I agree with teemuk on how to fix C5 & 7.
It is important to have the CCS's and cascode references free from AC. Zeners are good for this, but do gererate some noise. However, imagine the rails have fluctuation from the PS filter or from the output current. The zeners, D11 & D12, will have steady 4.7V across them but the power supply ripple voltage will still be on R18 & R19, and thus the base of Q's 17 & 21. You want to eliminate this AC with respect to GND, not the rails. IMO, a self bias J-fet CCS, a resistor, and a small cap is a better reference because the voltage is dependent on a steady current, not just a zener voltage reference. But I suggest keeping it as is here for simplicity and understanding. Maybe change the placement of the zeners and R18/19 and use a 45V zener and like 3K for the resistors?
CBS,
How should I eliminate AC ripple from the base of Q21 & Q17? I mean that one possible solution might be adding more capacitance from rails to ground, but since C9 & C10 are needed, I should do something that effects on those bases. How about adding capacitors in parallel with R18 & R19? Just in order to pass ac current to ground through the cap, not through R18 & R19. I also though adding resistors in series with the caps 9 & 10, but their values should be quite large so that major part of the ac voltage would be over them instead of R18 & R19.
But the basic issue is still: am I using totally false topologies as darkfenriz kindly suggested? According to the posts I have been reading, there are many opinions concerning these basic blocks, but I found no clear reason not to use this. I mean that although my circuit isn't complete yet, it may be someday.
Thanks again!
edit: You mean using the zeners between base and ground? Will try.
How should I eliminate AC ripple from the base of Q21 & Q17? I mean that one possible solution might be adding more capacitance from rails to ground, but since C9 & C10 are needed, I should do something that effects on those bases. How about adding capacitors in parallel with R18 & R19? Just in order to pass ac current to ground through the cap, not through R18 & R19. I also though adding resistors in series with the caps 9 & 10, but their values should be quite large so that major part of the ac voltage would be over them instead of R18 & R19.
But the basic issue is still: am I using totally false topologies as darkfenriz kindly suggested? According to the posts I have been reading, there are many opinions concerning these basic blocks, but I found no clear reason not to use this. I mean that although my circuit isn't complete yet, it may be someday.
Thanks again!
edit: You mean using the zeners between base and ground? Will try.
Hi Bootstrapper
If you take Q17 away from the circuit to 'simplify' its operation, you will see that Q17 is actually a common base amplifier. That is, the input signal to the emitter, the collector is the output, and the base is common. If you add a separate signal to the base with respect to the emitter, you create a modulator at the collector. Since this is not the desired result, the base must be common(AC) with ground. The zener will have constant voltage but not constant current, i e ripple voltage seen across R18/19. If you use the 45V zener from the base of Q17 to GND, there will be a constant voltage from there to GND. There is no need for a capacitor on the resistor as its voltage can fluctuate with the PS ripple and not affect the cascode reference voltage. A cap from the bases to ground || zener is a good thing, the goal is to conduct away the AC and zener noise.
The self bias J-fet creates a constant current. This constant current will, by Ohm's law, create a constant voltage across a resistor. A small cap || with the resistor will also help with noise. If you replaced the two zeners with self-biased J-fet's, move the caps to || R18/19, there shouldn't be any PS noise on the bases of Q17/21. You may have to measure the J-fet's to match more closely Vgs@Id, but it isn't that difficult, just time consuming.
If you take Q17 away from the circuit to 'simplify' its operation, you will see that Q17 is actually a common base amplifier. That is, the input signal to the emitter, the collector is the output, and the base is common. If you add a separate signal to the base with respect to the emitter, you create a modulator at the collector. Since this is not the desired result, the base must be common(AC) with ground. The zener will have constant voltage but not constant current, i e ripple voltage seen across R18/19. If you use the 45V zener from the base of Q17 to GND, there will be a constant voltage from there to GND. There is no need for a capacitor on the resistor as its voltage can fluctuate with the PS ripple and not affect the cascode reference voltage. A cap from the bases to ground || zener is a good thing, the goal is to conduct away the AC and zener noise.
The self bias J-fet creates a constant current. This constant current will, by Ohm's law, create a constant voltage across a resistor. A small cap || with the resistor will also help with noise. If you replaced the two zeners with self-biased J-fet's, move the caps to || R18/19, there shouldn't be any PS noise on the bases of Q17/21. You may have to measure the J-fet's to match more closely Vgs@Id, but it isn't that difficult, just time consuming.
Now that we are discussing about ripple voltage, and placement of just a couple of components, how do you feel about the rest of the design? Is the situation as hopeless as darkfenriz wrote?
Forgive me if I seem to be stubborn, but how about just adding a cap between Q21/Q17 base and ground, and leave the 4.7V Zener and everything else untouched? Since I cannot see the point in changing those zeners - they are still connected to the base And we still have those caps between rails and bases.
Thanks.
Forgive me if I seem to be stubborn, but how about just adding a cap between Q21/Q17 base and ground, and leave the 4.7V Zener and everything else untouched? Since I cannot see the point in changing those zeners - they are still connected to the base And we still have those caps between rails and bases.
Thanks.
Bootstrapper said:
I think the point he is making is that there is no DC reference for the opposing VAS transistors. IOW, by using current mirrors instead of resistors as a load for the LTP's, there is no set DC bias for Q's 14 & 7. I'm afraid it is in fact flawed in this manner.
But resistors are cheaper and simpler anyway.
And R18/19 still has ripple current through them. The zener will not have a constant current, only a constant voltage. With the voltage changing as the ripple on the power rails, this AC current will appear as voltage on R18/19, respect to GND. The only way to really have a constant DC voltage on R18/19 the way they are now is to have a constant current flowing through them.
5 mA through each of the input transistors is way two high for the part number you pick. Power dissipation will be about 245mW each. Increase R11 & R14 to 330 ohm to bring the current down to 1 mA.
At the same time, you may increase R3 R4 R5 & R6 to 470 ohm for the same amount of degeneration and thermal stability.
Also, connect a 10K 1W from emitter of Q17 to ground. Do the same to Q21. This will reduce the distortion by 2 to 4 dB.
Hope this help.
At the same time, you may increase R3 R4 R5 & R6 to 470 ohm for the same amount of degeneration and thermal stability.
Also, connect a 10K 1W from emitter of Q17 to ground. Do the same to Q21. This will reduce the distortion by 2 to 4 dB.
Hope this help.
I intended to use TO-92 package, which can handle over 600 mW at 25 degrees, so I would say that 200 mW is well within the safe margin. Transistors Q13 & Q6 meet the power limit sooner than those at the current mirrors.
As far as I know, larger bias currents in the input stage help to decrease distortion, make the circuit "faster" and also reduce the effects of the stray capacitances. But I guess the bias currents are not so critical as the mirrors, which I'm gonna remove soon.
Interesting idea of adding resistors from the VAS transistors to ground, what's the purpose of it? It surely works, I'm just curious
So far I've been suggested following improvements:
-remove current mirrors, replace with resistors
-add resistors from the Q17 & Q21 emitters to ground
-switch the places of R18 & D11 and R19 & D12 + change values
-add caps from the Q17 & Q21 bases to ground.
-split resistor R16 into four and connect C5 & C7 from the rails between two resistors and connect the junction of the two middle resistors to gnd. Just as teemuk suggested.
I will keep in mind that fet-option, but I'd like to try these first.
Definetely!
Hello again,
After doing previously mentioned changes, I found out following: If I use those 10k resistors in parallel with 43 V zeners, the current through zeners is something like 10 nA or so. That means the voltage across zeners is about 30 V instead of 43 V. So I decided not to add those resistors. That may increase distortion, but I have to get those zeners working properly. I'm not sure if circuitscc meant to use those extra resistors when the zeners are posititoned like they are at the post #1 pdf file.
The whole circuit behaves nicely, if I can trust those graphs given by pspice. I will add an upgraded schematics when I get home. It would be nice to have opinions on that as well
After doing previously mentioned changes, I found out following: If I use those 10k resistors in parallel with 43 V zeners, the current through zeners is something like 10 nA or so. That means the voltage across zeners is about 30 V instead of 43 V. So I decided not to add those resistors. That may increase distortion, but I have to get those zeners working properly. I'm not sure if circuitscc meant to use those extra resistors when the zeners are posititoned like they are at the post #1 pdf file.
The whole circuit behaves nicely, if I can trust those graphs given by pspice. I will add an upgraded schematics when I get home. It would be nice to have opinions on that as well
Q8 & Q16 see almost rail to rail voltage swing.
BC546 will not do. They can only take a max of 65Vce.
They will see around 90Vce to 95Vce when near clipping with normal mains voltage.
If mains voltage rises to maximum tolerance these and the other rail to rail transistors can see upto about 105Vce. Use at least 120Vce0 transistors and check temp derated SOAR at worst case reactive loadings.
C4 & R2 will cut your bass signal significantly. You have 19mS I reckon on about 90mS. Similarly C6 & R13 are a bit close to the input filter frequency. Try a ratio >=1.4
BC546 will not do. They can only take a max of 65Vce.
They will see around 90Vce to 95Vce when near clipping with normal mains voltage.
If mains voltage rises to maximum tolerance these and the other rail to rail transistors can see upto about 105Vce. Use at least 120Vce0 transistors and check temp derated SOAR at worst case reactive loadings.
C4 & R2 will cut your bass signal significantly. You have 19mS I reckon on about 90mS. Similarly C6 & R13 are a bit close to the input filter frequency. Try a ratio >=1.4
Hi,
I don't understand the discussion on the need to reduce or eliminate the decoupling on the cascodes and voltage references. I see recommendations for keeping one as is and fundamentally altering the other.
The idea of the cascode is for a constant voltage across the amplifying transistor. The amplifying transistor is connected to the supply rail and sees all the supply rail ripples and modulations.
I think the cascode should exactly follow these modulations as closely as possible and hold the base of the cascode and consequently the emitter at a fixed voltage across the respective transistor.
Similarly, for the voltage reference that ensures constant current in the transistor setting the LTP tail current. The voltage from base to rail must be as fixed as possible to prevent modulation of the CCS current.
Convince me I'm wrong.
I don't understand the discussion on the need to reduce or eliminate the decoupling on the cascodes and voltage references. I see recommendations for keeping one as is and fundamentally altering the other.
The idea of the cascode is for a constant voltage across the amplifying transistor. The amplifying transistor is connected to the supply rail and sees all the supply rail ripples and modulations.
I think the cascode should exactly follow these modulations as closely as possible and hold the base of the cascode and consequently the emitter at a fixed voltage across the respective transistor.
Similarly, for the voltage reference that ensures constant current in the transistor setting the LTP tail current. The voltage from base to rail must be as fixed as possible to prevent modulation of the CCS current.
Convince me I'm wrong.
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