DC-offset problem

[Bootstrapper]

I'm attending a course on audioelectronics and we have a following exercise to do for grading. We were given complete schematic of an amplifier and we were to find out component values so that the circuit would fill certain specifications. Meeting the rest of the requirements was quite easy, only getting dc offset below 50 mV seems to be too difficult.

Can anyone give a hint (or several) based on this information? I don't want to get complete solution, I need hints to find the solution on my own. My time is short right now, so I will post a new message with additional information as soon as I have time.

Thanks in advance!

 

[gni]

We need to see the schematic:

 

[Donk]

Dear Bootstrapper,

Without knowing the exact topology or the basic set-up of that amplifier it's impossible to suggest whatever.
If the amplifier is designed along the conventional three-stage Lin-topology than I would advise to look into the feedback path and the differential amplifier stage (LTP).
More information about the amplifier or even a complete schematic would help us a lot to find out the problem related to high DC offset.


Best regards,

Donk

 

[Bootstrapper]

It's always nice to reply to your own posts - you will usually get answers you like to get For some reason the circuit is not visible, so I will include direct link to it. As for the problem I had, few minutes after I posted here, I received the answer. Typical. Considering this circuit, it is most important that the impedances from the differential pair transistor bases to ground be as equal as possible to ensure low dc offset at the output. Another solution would be adding a capacitor (I used 47 uF) between ground and the parallel resistor (R8) in the feedback loop. This method of dc-isolating the feedback loop proved to be most lovely, since after adding the capacitor, I got approx. 17 uV offset! Very nice and simultaneously the bias currents in the small signal stage moved even closer to each other.

Perhaps somebody will find this information useful, unless I am the only one who wasn't aware of these tricks. Anyway, the circuit can be found here:
30 W amplifier

 

[Donk]

Hi Bootsrapper,

Thanks for posting the schematic. As I vaticinated it's a conventional Lin-topology amplifier.

Let me suggest some modification:

1., R4's value need to be equal with R27's
2., R37 is too large, try 100 Ohm instead
3., A Zobel-network on the output of the amplifier is needed (10 Ohm + 100nF in serial)
4., Using of triple-darlington in the OP stage is pointless IMHO
5., Resistor values in the protection circuit are false
6., A bypass cap over the Vbe-ultiplier would be great

Best regards,

 

[Bootstrapper]

Few comments on your reply:

1. R4's value need to be equal with R27's

Like I wrote, I was told that the base-to-ground impedances of the transistors Q15 & Q16 should be as equal as possible. Personally I don't no much about this precise subject, so I cannot say anything about your idea. It might well work, I surely will test that.

2. R37 is too large, try 100 Ohm instead

That may be correct. I did not give much thoughts about resistors R10 and R37, because I fixed the bias currents with other components. As far as I know, these resistors R10 and R37 can be used to define the bias currents of the four power transistors. If they have other uses, I need to find them out.

3. A Zobel-network on the output of the amplifier is needed (10 Ohm + 100nF in serial)

I am well aware of Zobel network, and also using (small) parallel resistor and coil is series with the output, but in this exercise the schematic was given ready, and we were not allowed to alter it.

4. Using of triple-darlington in the OP stage is pointless IMHO

According to the specifications given with the exercise, reasons for such an output topology were the following: "Adding one EF stage reduces loading at the collector of Q13. It also helps to get more gain and also reduces loads effects on this point. Simultaneously the required base current drive capability for larger output current will be met."

5. Resistor values in the protection circuit are false

They should be correct, since the required current limit was 5 A. So, when that current goes through R7, it will generate voltage of 5 volts across R7. The voltage across R41 needs to be about 0.7 volts to make the current limiter active. Then we can use the voltage divider rule and calculate the ratio R36/R41. It will become approx. 6. So we can choose following resistor values: R36=12k, R41=2k. Using PSpice I verified that the current limiter worked fine: I had a 10 mF cap at the output instead of 8 ohm resistor and I used slowly rising square wave as the input signal. Measuring the load capacitor current and the voltage across it showed that the limiter was working fine. Where did I make mistake?

6. A bypass cap over the Vbe-ultiplier would be great

Yes, I've seen it in many circuits, for example in those designed by monsieur Self. Though it might be great, we cannot alter this circuit for the reason I already explained.

Thanks for your post!!

 

[CBS240]

Like I wrote, I was told that the base-to-ground impedances of the transistors Q15 & Q16 should be as equal as possible.
I agree with this statement. Shouldn't R8 should be equal to R27? I would also lower R27 to 1K, 47K is too large here. A DC blocking cap would help with the DC offset between R8 and GND. But since you arn't allowed to change the circuit, DC offset will be affected by any mis-matching of Q15/Q16, and gain.

2. R37 is too large, try 100 Ohm instead

There will be 1.2V across R37 due to the Vbe drops of Q5/Q6, you decide how much current you want bias in Q7/Q8. 1.2V/R=I
R10 will have 4 Vbe drops across it so it's value will be 2.4V/R=I.
I would go a milliamp or so with Q9/Q10, maybe 10mA with Q7/Q8.

R3 and R17 should be equal to get even clipping.

4. Using of triple-darlington in the OP stage is pointless IMHO
IMO, this circuit will probably not be the fastest circuit in the world. Tripple darlington increases current gain, so there is less load on the VAS. So using a tripple darlington surrounded by GNF(global negative feedback)here, shouldn't make that big a difference in bandwidth after frequency compensation. Speaking of compensation, how did you derive C1 and C2?

5. Resistor values in the protection circuit are false

They should be correct, since the required current limit was 5 A. So, when that current goes through R7, it will generate voltage of 5 volts across R7. The voltage across R41 needs to be about 0.7 volts to make the current limiter active. Then we can use the voltage divider rule and calculate the ratio R36/R41. It will become approx. 6. So we can choose following resistor values: R36=12k, R41=2k. Using PSpice I verified that the current limiter worked fine: I had a 10 mF cap at the output instead of 8 ohm resistor and I used slowly rising square wave as the input signal. Measuring the load capacitor current and the voltage across it showed that the limiter was working fine. Where did I make mistake?

So when there is 5A conducting, you lose 5V in R7 or 13, plus the saturation voltage of the transistor from the maximum output signal level. This seems kinda like a waste don't you think? I would use something like 0.2 or 0.3 Ohms for these.


The Vbe multiplier looks funny. If the base of Q1 is connected to the wiper of the pot, this is not good. If the pot fails with an open wiper, Q1 will turn off, and the outputs will saturate and release thier magic smoke. The pot should be from the base to emitter of Q1.

 

[AndrewT]

Hi,
the Vbe multiplier needs attention. Check R6. Is RP1 & 2 a pot at half value? Move as said previously.
The driver Re needs attention
The parallel combination of R4//R8 is different from the Parallel combination of R27//(R28+c5).
Why are R16=R17?
With output current limiting, what happens when either Q11 or Q12 triggers? I see a dead short between output and Q13 collector. What do you see? and then what happens?

 

[teemuk]

Shouldn't R8 should be equal to R27?

I believe this is true when the ground shunt of negative feedback path (R8) does not use capacitive coupling. However, in case a series capacitor is used with R8 (which, in my experience, will provide a lower DC offset then omitting it) R4 = R27 and R8 = R28.

Isn't C6 a bit too small? ...And gain of 10 (R4 / R8 +1) is too low as well?

 

[Bootstrapper]

Seems this issue starts escalating out of my control (as well as understanding)!

Considering the feedback loop, we see that to obtain similar impedances from diff.pair bases to ground, R27 must be equal to R4 (since R4 if effectively between transistor base and ground; it has load impedance in series - that is approx. 0 ohm compared to 9k). But this requires that R8 is not between base and ground, or the total impedance would be R8 || R24 (parallel). It is not visible in current picture, but right now I have 22 uF cap between R8 and ground - this change was suggested by the person quiding this exercise.

CBS240, do you mean that by having too large R7 & R13 maximum output voltage will be limited? Power loss in those resistors should not be an issue as far as I know (since it is quite low). Caps C1 and C2 were specified after simulating, to meet the required stability demands and also the upper -3dB point. By the way, thanks for sharing the information about positionign the pot correctly at the vbe multiplier, I will remember this.

Andrew, I know R6 is quite large, but I decided to use that after simulations, I haven't found reason to alter it. Could you tell me if it is absolutely too large and why? I cannot move the vbe multiplier pot. And I have already lowered R37. I also see that when Q11 conducts, there is straight path to ground from Q13 collector via D1 and Q11. What happens then? Well, there's virtually nothing to limit the current so I expect both Q13 and Q11 to be destroyed. But alas, I still cannot change the circuit! R.Slone has used a 15-ohm resistor in that path, that would perhaps do good.

teemuk, C6 is actually 1 uF, I have been constantly deleting and adding that cap due to square wave simulations. I just forgot to change the value. Also the gain of whole circuit should be 20 dB, that's the reason for the feedback resistor values.

Thanks you all, I got again invaluable information!

 

[CBS240]

CBS240, do you mean that by having too large R7 & R13 maximum output voltage will be limited? Power loss in those resistors should not be an issue as far as I know (since it is quite low).

Hi

Yes. When the signal is peak, there would be 5A through 1 Ohm, and that makes 5V. The goal is to have rail to rail voltage swing because the less voltage left in the circuit, the less power in heat it has to dissapate. There may be a couple of volts on the transistor too so that is like 7 potential volts missing from the output. These resistors are degeneration resistors. R7 & R13 are a form of negative feedback for the output transistors. If they are too large, you lose voltage gain in the follower at the output node. They also limit current for protection since BJT's can have a very high conductance so there is still need for them.

 

[Mooly]

Q15/Q16 to be matched and in thermal contact with each other.

 

[AndrewT]

Considering the feedback loop, we see that to obtain similar impedances from diff.pair bases to ground, R27 must be equal to R4 (since R4 if effectively between transistor base and ground; it has load impedance in series - that is approx. 0 ohm compared to 9k). But this requires that R8 is not between base and ground, or the total impedance would be R8 || R24 (parallel). It is not visible in current picture, but right now I have 22 uF cap between R8 and ground - this change was suggested by the person quiding this exercise.

I know R6 is quite large, but I decided to use that after simulations, I haven't found reason to alter it. Could you tell me if it is absolutely too large and why? I cannot move the vbe multiplier pot. And I have already lowered R37. I also see that when Q11 conducts, there is straight path to ground from Q13 collector via D1 and Q11. What happens then? Well, there's virtually nothing to limit the current so I expect both Q13 and Q11 to be destroyed.

Hi,
if the two sides of the input long tail pair (LTP) are to be balanced for least output offset and least output offset drift then DC blocking caps must be fitted to both the input from the source and also to the lower leg of the NFB loop. Or no DC blocking caps to either side of the LTP. NOT mixed DC blocking/AC coupling.

The driver emitter resistor determines the driver bias (quiescent) current. If this is set very low the driver turns off very early in the amplification process. I don't have data/research to back up this next assertion but I think the driver should stay in ClassA longer than the output devices before each stage starts to go into ClassAB as output currents rise.


Q11 develops a low voltage across it when it triggers. This allows very large currents to flow without risk of damage to Q11.
But Q13 starts to develop a very large voltage across it and also increasing current flows. The power dissipated in the junction can be considerable for the brief period that the protection transistor conducts. The string R3, Q13, D1, Q11 connects Vrail to output and a short or failed output device connects to either ground or the opposite Vrail. Calculate the Vdrops across each device and estimate the fault current that will flow. You can now estimate the dissipation across each device and see which are most at risk of damage, not necessarily destruction.