DC-offset problem

[CBS240]

Originally posted by Bootstrapper
CBS240, do you mean that by having too large R7 & R13 maximum output voltage will be limited? Power loss in those resistors should not be an issue as far as I know (since it is quite low).

Hi

Yes. When the signal is peak, there would be 5A through 1 Ohm, and that makes 5V. The goal is to have rail to rail voltage swing because the less voltage left in the circuit, the less power in heat it has to dissapate. There may be a couple of volts on the transistor too so that is like 7 potential volts missing from the output. These resistors are degeneration resistors. R7 & R13 are a form of negative feedback for the output transistors. If they are too large, you lose voltage gain in the follower at the output node. They also limit current for protection since BJT's can have a very high conductance so there is still need for them.

[Mooly]

Q15/Q16 to be matched and in thermal contact with each other.

[AndrewT]

Originally posted by Bootstrapper
Considering the feedback loop, we see that to obtain similar impedances from diff.pair bases to ground, R27 must be equal to R4 (since R4 if effectively between transistor base and ground; it has load impedance in series - that is approx. 0 ohm compared to 9k). But this requires that R8 is not between base and ground, or the total impedance would be R8 || R24 (parallel). It is not visible in current picture, but right now I have 22 uF cap between R8 and ground - this change was suggested by the person quiding this exercise.

I know R6 is quite large, but I decided to use that after simulations, I haven't found reason to alter it. Could you tell me if it is absolutely too large and why? I cannot move the vbe multiplier pot. And I have already lowered R37. I also see that when Q11 conducts, there is straight path to ground from Q13 collector via D1 and Q11. What happens then? Well, there's virtually nothing to limit the current so I expect both Q13 and Q11 to be destroyed.

Hi,
if the two sides of the input long tail pair (LTP) are to be balanced for least output offset and least output offset drift then DC blocking caps must be fitted to both the input from the source and also to the lower leg of the NFB loop. Or no DC blocking caps to either side of the LTP. NOT mixed DC blocking/AC coupling.

The driver emitter resistor determines the driver bias (quiescent) current. If this is set very low the driver turns off very early in the amplification process. I don't have data/research to back up this next assertion but I think the driver should stay in ClassA longer than the output devices before each stage starts to go into ClassAB as output currents rise.


Q11 develops a low voltage across it when it triggers. This allows very large currents to flow without risk of damage to Q11.
But Q13 starts to develop a very large voltage across it and also increasing current flows. The power dissipated in the junction can be considerable for the brief period that the protection transistor conducts. The string R3, Q13, D1, Q11 connects Vrail to output and a short or failed output device connects to either ground or the opposite Vrail. Calculate the Vdrops across each device and estimate the fault current that will flow. You can now estimate the dissipation across each device and see which are most at risk of damage, not necessarily destruction.