Hi,
How does one test for Vce0, if possible without destroying the device.
I just tried feeding voltage through 2M2 to the collector of bc549b and measuring Ic with b to e shorted. bc549b is 30Vce0 minimum.
Got upto 63Vce and still no reading across 2M2 @ 0.1mV resolution.
Rechecked hFE in the DMM and it still read 209 to 211 depending on temperature.
I think the input impedance of my meter has dropped from 1M to 250k at the lowest scale, but working back that seems to indicate that Ic<0.4nA. Surely this is too low at double the rated voltage.
How should I do this?
How does one test for Vce0, if possible without destroying the device.
I just tried feeding voltage through 2M2 to the collector of bc549b and measuring Ic with b to e shorted. bc549b is 30Vce0 minimum.
Got upto 63Vce and still no reading across 2M2 @ 0.1mV resolution.
Rechecked hFE in the DMM and it still read 209 to 211 depending on temperature.
I think the input impedance of my meter has dropped from 1M to 250k at the lowest scale, but working back that seems to indicate that Ic<0.4nA. Surely this is too low at double the rated voltage.
How should I do this?
You are pretty much doing it the way it's usually done. Also, do not be surprised at the results, they are typical. Try heating up the transistor's case with a soldering iron to see something interesting 
Also, you will usually notice that PNP transistors exhibit much less 'headroom' than their NPN counterparts.
In any case, you should limit the current to a very small fraction of what one would expect looking at the DC SOA (or just calculating from Pdiss). I remember once frying a perfectly genuine 2SA1216 testing Vceo (to determine if it was a fake) by forgetting to limit the current of my HV power supply. It should be noted that the maximum current (when limiting is off) is only 50mA, and having reached some 250V at which it broke down, I promptly destroyed the part (permanent short C-E) - keep in mind a 2SA1216 is a really huge transistor.
Also, you will usually notice that PNP transistors exhibit much less 'headroom' than their NPN counterparts.
In any case, you should limit the current to a very small fraction of what one would expect looking at the DC SOA (or just calculating from Pdiss). I remember once frying a perfectly genuine 2SA1216 testing Vceo (to determine if it was a fake) by forgetting to limit the current of my HV power supply. It should be noted that the maximum current (when limiting is off) is only 50mA, and having reached some 250V at which it broke down, I promptly destroyed the part (permanent short C-E) - keep in mind a 2SA1216 is a really huge transistor.
Hi
are you describing an avalanche failure?
I was expecting to see a gradual increase in Ic as I went over the rated voltage. Maybe I should arrange a 100Vdc for my 30V test device and that below.
I wanted to check some BC546c to see if they would be reliable at 60Vdc, ensuring I had a margin for unexpected voltage excursions.
are you describing an avalanche failure?
I was expecting to see a gradual increase in Ic as I went over the rated voltage. Maybe I should arrange a 100Vdc for my 30V test device and that below.
I wanted to check some BC546c to see if they would be reliable at 60Vdc, ensuring I had a margin for unexpected voltage excursions.
Vceo is different from Vce(sus)
NPN power BJTs exhibit an avalanche effect when going into CE breakdown. PNPs to not exhibit avalanche.
With the Base shorted to the Emitter we find the highest breakdown voltage, Vces. This is normally tested at 10uA constant current and can usually be done at DC since the device dissipation is nor excessive.
What happens with Vceo is that as the device starts to breakdown, current is diverted into the base region turning the device parially on, lowering the breakdown voltage. A better understanding needs a knowledge of semiconductor physices, which I forgot 30 years ago.
Vce(sus) is normally tested at 100mA or above. Now the problems start since the breakdown at DC for this current will normaly kill the device almost instantly.
In addition there is a negative resistance region between Vces and Vce(sus) of some 30 to 50 volts which will cause wild oscillation in most test circuits, contributing further to destruction.
There is a correct and safe way to test it using fast pulses and a "trick".
The trick is to saturate the transistor on with IC = 100mA (the Vce(sus) constant current. This is done with an Ib of typically Ic/5 = 20mA.
The base is then opened (using a mercury wetted relay) and the collector will then fly up into the avalanche voltage without passing through the negative resistance region. A S&H circuit then measures this voltage and the current pulse is terminated.
The current pulse is 300uS wide and the duty cycle (for repeated measuremets) is < 2% to avoid heating.
Not easy to do this on the bench
NPN power BJTs exhibit an avalanche effect when going into CE breakdown. PNPs to not exhibit avalanche.
With the Base shorted to the Emitter we find the highest breakdown voltage, Vces. This is normally tested at 10uA constant current and can usually be done at DC since the device dissipation is nor excessive.
What happens with Vceo is that as the device starts to breakdown, current is diverted into the base region turning the device parially on, lowering the breakdown voltage. A better understanding needs a knowledge of semiconductor physices, which I forgot 30 years ago.
Vce(sus) is normally tested at 100mA or above. Now the problems start since the breakdown at DC for this current will normaly kill the device almost instantly.
In addition there is a negative resistance region between Vces and Vce(sus) of some 30 to 50 volts which will cause wild oscillation in most test circuits, contributing further to destruction.
There is a correct and safe way to test it using fast pulses and a "trick".
The trick is to saturate the transistor on with IC = 100mA (the Vce(sus) constant current. This is done with an Ib of typically Ic/5 = 20mA.
The base is then opened (using a mercury wetted relay) and the collector will then fly up into the avalanche voltage without passing through the negative resistance region. A S&H circuit then measures this voltage and the current pulse is terminated.
The current pulse is 300uS wide and the duty cycle (for repeated measuremets) is < 2% to avoid heating.
Not easy to do this on the bench
Hi Cliff,
if my operating condition were Ic=1.6mA and Vce=50V.
Are you saying that testing Vce0 with base to emitter shorted proves nothing of value?
If the transistors passed the 60+20% (72Vce0) and the hFE did not change, does that show the transistors are likely to survive 50Vce +- operational swings?
if my operating condition were Ic=1.6mA and Vce=50V.
Are you saying that testing Vce0 with base to emitter shorted proves nothing of value?
If the transistors passed the 60+20% (72Vce0) and the hFE did not change, does that show the transistors are likely to survive 50Vce +- operational swings?
I don't think you have a problem - I was only trying to describe how BJTs are factory tested. How this relates to any particular application is not so easy.
The Vce(sus) rating is really important when considering SOA, particularly with switching inductive loads, where it is very easy to go from saturation to avalanche breakdown in microseconds. In such a case zener snubbing across the CE at less than Vce(sus) is required.
In linear applications as long as the maximum possible excursion is less than Vceo there are no worries at all. Less than Vces is also OK, but I would start to worry with difficult speaker loads for reasons we all know about.
Once again, this normally does not have relevance in small signal applications, but is the whole reason for the emphasis on SOA curves in power devices. Also be aware of the importance of the base connection (short or open) when trying to measure CE breakdown.
I spent many years in semi test for Fairchild - in its original iteration ie a ling time ago!
The Vce(sus) rating is really important when considering SOA, particularly with switching inductive loads, where it is very easy to go from saturation to avalanche breakdown in microseconds. In such a case zener snubbing across the CE at less than Vce(sus) is required.
In linear applications as long as the maximum possible excursion is less than Vceo there are no worries at all. Less than Vces is also OK, but I would start to worry with difficult speaker loads for reasons we all know about.
Once again, this normally does not have relevance in small signal applications, but is the whole reason for the emphasis on SOA curves in power devices. Also be aware of the importance of the base connection (short or open) when trying to measure CE breakdown.
I spent many years in semi test for Fairchild - in its original iteration
ie a ling time ago!And to re-read your original message:
The reverse current will usually be sub nA for small geometry devices, rising with temperature but not with voltage, ie it is not simply resistive.
When the breakdown region is reached it will of course rise extremely rapidly.
So I am not suprised at your leakage reading.
You will need a much higher supply in constant current mode (aim for 10uA) to measure the breakdown, putting the DVM across the lower leg of 99MR/1MR pot divider across CE.
If you want some 0.1% 100MR resistors, send me you address by email. I still have a huge collection of precision parts.
The reverse current will usually be sub nA for small geometry devices, rising with temperature but not with voltage, ie it is not simply resistive.
When the breakdown region is reached it will of course rise extremely rapidly.
So I am not suprised at your leakage reading.
You will need a much higher supply in constant current mode (aim for 10uA) to measure the breakdown, putting the DVM across the lower leg of 99MR/1MR pot divider across CE.
If you want some 0.1% 100MR resistors, send me you address by email. I still have a huge collection of precision parts.
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