Symmetrical differential vs symmetrical non-differential VAS

[PB2]

Glen, you are riight on here.

Mosfet capacitances:

Ciss=Cgs+Cgd.
Coss=Cds+Cgd
Crss= Cgd

The capacitances are quite significant, load dependant - IOW
if the OP stage drives 8R effective Ciss as seen by VAS will be
different compared to 4R as there will be more voltage swing
between g-s. Add to this the fact that they are also voltage
dependant and non linear.

Main reason why I suggested a bjt small sig driver in front of
them.

Also it is worth mentioning here that lifting the 'opposite side'
VAS collectors off ground has little chance of working in reality. It
consitutes two CCS balancing each other. They will most
likely clip or simply drift way off nominal.

Geez - I'm starting to sound like a grumpy old fart.... must be
over training / undersleeping.

Terry

I was certainly aware of the FET capacitances, and again if roughly matching with a 4 ohm load works with low enough distortion with 2 to 16 ohm loads then what is the fuss?

You claim that lifting the "opposite side" will clip or drift and this was why I suggested a load to ground, did you miss that?
They are not CCS's, rather they are driven complementary current sources and their behavior depends on the drive from the previous stage. I don't expect any problem especially if an RC load is used.

Pete B.

 

[Terry Demol]

I was certainly aware of the FET capacitances, and again if roughly matching with a 4 ohm load works with low enough distortion with 2 to 16 ohm loads then what is the fuss?

Pete,

Yes, I am sure you are (aware).

My comment WRT FET capacitances is in support of Glens statement
and in question of Suzy's capacitance values mentioned in post 12.
They didn't appear to come anywhere close to the real thing which
is of much higher value and hugely variable with swing and load.

So the hypothesis of matching VAS loads causing lower THD may
not be what is happening.

You claim that lifting the "opposite side" will clip or drift and this was why I suggested a load to ground, did you miss that?

Again, not referring to your post. Suzy's post 12 indicates the
collectors were only connected to each other and had no reference
to ground.

I thought I would point out the real world implications of such an
arrangement of two collector OP's balancing each other as no one
else had questioned it.

cheers

Terry

 

[suzyj]

My comment WRT FET capacitances is in support of Glens statement
and in question of Suzy's capacitance values mentioned in post 12.
They didn't appear to come anywhere close to the real thing which
is of much higher value and hugely variable with swing and load.

Ummm, I might be totally wrong here, but given that the MOSFETs are connected as followers, then surely only Cgd counts?

Again, not referring to your post. Suzy's post 12 indicates the
collectors were only connected to each other and had no reference
to ground.

I thought I would point out the real world implications of such an
arrangement of two collector OP's balancing each other as no one
else had questioned it.

Don't forget though that the whole thing is wrapped in a feedback loop, which is DC coupled. This I think will keep the voltages on either side of the VAS honest.

 

[GK]

Ummm, I might be totally wrong here, but given that the MOSFETs are connected as followers, then surely only Cgd counts?

Nope. The effective capacitance to ground, as seen at the gate of a source follower is approximately equal to Cin = Cgd + Cgs*(1 - Av). Cgd only plays a minor role at high Id as Cgs is huge in comparison and varies wildly with Id. More Id = more input capacitance. This makes any attempt to load match the VAS on the unused side with an RC circuit practically worthless, IMO.

Don't forget though that the whole thing is wrapped in a feedback loop, which is DC coupled. This I think will keep the voltages on either side of the VAS honest.

Does not matter one jot. The unused side of the differential VAS is effectively outside of the global NFB loop and without a reference to ground there is absolutely nothing to define the collector voltage on the unused side.
Think about the operation of the differential VAS on the side driving the MOSFETs. For a positive signal swing the PNP BJT conducts more current while the NPN BJT conducts less current – and vice versa for negative swings. Now for balanced operation of the differential VAS, this behaviour has to be complemented on the other side. With both the PNP and the NPN transistor sharing a common collector connection/current, how on earth is that possible? When the NPN needs to conduct more current than the PNP, from where is it going to get its current? From the PNP? Duh.

BTW, have you atleast tried a sim with the VAS cascoded? I think that you might be surprised by the results. Here is a primer on the value of cascoding large signal amplifier stages (such as VA stages):

http://www.essex.ac.uk/ESE/research/audio_lab/malcolmspubdocs/J10 Enhanced cascode.pdf


Cheers,
Glen

 

[suzyj]

Nope. The effective capacitance to ground, as seen at the gate of a source follower is approximately equal to Cin = Cgd + Cgs*(1 - Av). Cgd only plays a minor role at high Id as Cgs is huge in comparison and varies wildly with Id. More Id = more input capacitance. This makes any attempt to load match the VAS on the unused side with an RC circuit practically worthless, IMO.

This was what I was getting at. For a source follower, Av ~= 1, so thus Cin ~= Cgd + (Cgs(1 - 1) ~= Cgd...

Indeed, this explains the use of these large MOSFETs only as source followers. If you try to get voltage gain with them, Cgs bites hard, and clobbers your slew rate.

Does not matter one jot. The unused side of the differential VAS is effectively outside of the global NFB loop and without a reference to ground there is absolutely nothing to define the collector voltage on the unused side.

The VAS here is a difference amplifier. The voltage on one side is the mirror of the voltage on the other. The voltage on the load side is dictated by the feedback loop, so the voltage on the unused side will be the -ve of this.

BTW, have you atleast tried a sim with the VAS cascoded? I think that you might be surprised by the results.[/B]

No, I haven't. I've tried isolating the MOSFETs from the VAS with source followers, which has very little effect, unless I use large numbers of MOSFETs (and hence have a large Cgd) but draw the line at that. Cascoding the VAS is completely nonsensical, as I'll have to add the cascode voltage to my supply, which makes the whole thing ridiculously inefficient.

You seem to have a real hang-up over gate capacitance. Do the math. Cin isn't nearly as big as you think.

 

[GK]

Originally posted by suzyj
This was what I was getting at. For a source follower, Av ~= 1, so thus Cin ~= Cgd + (Cgs(1 - 1) ~= Cgd...
Indeed, this explains the use of these large MOSFETs only as source followers. If you try to get voltage gain with them, Cgs bites hard, and clobbers your slew rate.


Sorry, with MOSFETs Av is significantly less than 1 - especially with Lateral MOSFETs due to their low transconductance - Cgs IS significant in the source follower configuration. This is particularly so at high Id.


The VAS here is a difference amplifier. The voltage on one side is the mirror of the voltage on the other. The voltage on the load side is dictated by the feedback loop, so the voltage on the unused side will be the -ve of this.


Only if the differential VAS is well balanced and the unused side sees an identical impedance to ground. If the collectors of the two BJTs on the unused side are simply connected together and left floating, this simply will not be the case, the voltage will be all over the place (the NPN and PNP alternately saturating) and the differential VAS simply cannot operate as a balanced circuit for the obvious reason I already outlined.


No, I haven't. I've tried isolating the MOSFETs from the VAS with source followers, which has very little effect, unless I use large numbers of MOSFETs (and hence have a large Cgd) but draw the line at that. Cascoding the VAS is completely nonsensical, as I'll have to add the cascode voltage to my supply, which makes the whole thing ridiculously inefficient.


You’re exaggerating a bit. The cascode voltage would only have to be a few volts, and anyway, I meant more as an exercise in SPICE to get a handle on the sources of distortion in large signal amplifying stages.
Any BJT amplifier stage will generate significant distortion if Vce sees large signal swings - due to a change in transconductance and non-linear NFB via Cob. This is explained clearly in the paper I linked too. It is where your differential VAS distortion is coming from. Also, for a practical implementation you would only need to add the cascode voltage to the rails of the low power circuitry, not the MOSFET output stage (a pair of low voltage supplies floating on the power output stage rails would do the trick).
In fact, if you’re are so worried about efficiency, you could add a few more volts to compensate for Vgs as well – then your amplifier would be even more efficient, cascoded ‘n all.


You seem to have a real hang-up over gate capacitance. Do the math. Cin isn't nearly as big as you think.

It is exactly as large as I think it is. Why don’t you do the math, considering MOSFET transconductance and the drop in Av.

Now I can give you another reason why attempting to load match the unused side of the VAS will with an R/C will not work reliably in a practical situation. You have to match the impedance over three frequency decades (20-200-2000-20k). At low frequencies, the impedance at the MOSFET side of the VAS will be very large. This means that your R on the other side will also have to be equally large.
The slightest Ic imbalance of the differential VAS due to spreads in component parameters will cause the collector voltage on the unused side to saturate. And no, the global NFB will not correct for this.

Cheers,
Glen

 

[PB2]

Glen you're exaggerating also, there is no issue with the LF distortion, just trying to improve the HF distortion, so there's no need to match the load over 3 decades or more as you claim.

Why don't you do the sim and show us since you seem to be taking such a strong position on this. Actually, I don't doubt that it will sim well, so why bother. I just can't see adding any more complexity that requires power supply changes on top of the basic change.

I'd go to the single ended VAS if it provided better performance in real hardware, rather than increasing complexity as you suggest, before I went to cascodes. But that's just my opinion as I have stated before.

Pete B.

 

[GK]

Glen you're exaggerating also, there is no issue with the LF distortion, just trying to improve the HF distortion, so there's no need to match the load over 3 decades or more as you claim.

Why don't you do the sim and show us since you seem to be taking such a strong position on this. Actually, I don't doubt that it will sim well, so why bother. I just can't see adding any more complexity that requires power supply changes on top of the basic change.

I'd go to the single ended VAS if it provided better performance in real hardware, rather than increasing complexity as you suggest, before I went to cascodes. But that's just my opinion as I have stated before.

Pete B.

Hmmm….In post 7 you wrote:

”I suggest a resistive load to match the diff VAS outputs at say 10 Hz, and a capacitor to match at 10 kHz, and then see if this is a good enough approximation.”

I really don’t think that I’m taking a very strong position on this; it just seems to be difficult to get a point across.
As far as I can see, the only practical way to get the symmetrical VAS to perform better than the single ended VAS is to cascode it. Wether this is all worthwhile or not is another question entirely and the other methods presented here are practically unworkable, IMHO.
Untying the unused VAS collectors from ground and leaving the floating simply cant work, and approximating the load on the unused side with an R//C looks unworkable to me for a multitude of reasons. These are problems are obvious, and I don’t need to run a sim to verify them.
There is the inescapable problem of Ic imbalance throwing the collector voltage on the unused side of the VAS towards the rails. Then there is the non-linear MOSFET input capacitance, which is highly variable with both load current and Vds. In order to avoid premature saturation (and distortion) of the unused side of the VAS, you would have to design your R//C load impedance match for the worst case peak load condition (which corresponds to the greatest peak current demand from the VAS).
This means that, during probably 99.99% of the amplifiers normal operation, the R//C circuit will simply not develop a signal voltage that is even a remotely useful complement of voltage on the MOSFET driving side of the VAS.


Cheers,
Glen

 

[PB2]

Hmmm….In post 7 you wrote:

”I suggest a resistive load to match the diff VAS outputs at say 10 Hz, and a capacitor to match at 10 kHz, and then see if this is a good enough approximation.”

I really don’t think that I’m taking a very strong position on this; it just seems to be difficult to get a point across.
As far as I can see, the only practical way to get the symmetrical VAS to perform better than the single ended VAS is to cascode it. Wether this is all worthwhile or not is another question entirely and the other methods presented here are practically unworkable, IMHO.
Untying the unused VAS collectors from ground and leaving the floating simply cant work, and approximating the load on the unused side with an R//C looks unworkable to me for a multitude of reasons. These are problems are obvious, and I don’t need to run a sim to verify them.
There is the inescapable problem of Ic imbalance throwing the collector voltage on the unused side of the VAS towards the rails. Then there is the non-linear MOSFET input capacitance, which is highly variable with both load current and Vds. In order to avoid premature saturation (and distortion) of the unused side of the VAS, you would have to design your R//C load impedance match for the worst case peak load condition (which corresponds to the greatest peak current demand from the VAS).
This means that, during probably 99.99% of the amplifiers normal operation, the R//C circuit will simply not develop a signal voltage that is even a remotely useful complement of voltage on the MOSFET driving side of the VAS.


Cheers,
Glen

Seems that there is a lot of repitition here, I heard you the first time, am aware of all the issues before you stated them, thanks. You got your point across and I am not accepting your perfectionist view point and solution as the only solution. We can agree to disagree, I have tried to several times.

You design for perfection and you think that you can simulate in your head. My suggestion was something to try, in simulation, and perhaps in the real circuit. This is casual conversation, and I'm valuing your opinion less, and less. Go ahead, see how many transistors you can add.

Glen, I've just about had enough, I have much better things to do than counter your untested claims. You are very sure of yourself, to the point of making discussion with you difficult. I'm going to drop it for now.

Pete B.

 

[GK]

You design for perfection and you think that you can simulate in your head.

Yep. I can see through women’s undergarments and communicate with the Daleks via mental telepathy too. I once accidentally wandered into the Senior Women’s Association bingo night venue. That was horrible.

Beep.

 

[CBS240]

Hi

In reading this thread, and some exp. in working with a similar circuit, I agree with Glen that the currents in the VAS diff will not be the same, in order for the circuit to act as a proper "mirror" for the "turn-off" phase, if the effective impeadance seen by each side is not the same. This impeadance must be equal for large band not just DC. It may be hard to simulate the load of the mosfets for the unused side, which brings up the question, could the complementary differential VAS be used to drive a bridged output topology, having the same effective load on each side...... The other option is to drive a single load(the mosfets) with the VAS as a cascode or not, or task to find a way to effectively make each impeadance the same, hence the idea of a bridged output.

my