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output impedance testing
output impedance testing
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Old 15th July 2007, 10:12 PM   #1
unclejed613 is offline unclejed613  United States
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Default output impedance testing

ok, i found out the ideal amplifier model in LTSpice has a small flaw. as a matter of fact it had an unexpected effect on my sim results, so i'm starting the whole process again with a different model. shown below are the original model, and the new model. the problem with the original model is that with the cap that sets GBW straight across the output, the GBW changes with low output impedances, so the new model on the right buffers the gain stage with a voltage controlled voltage source..... now it should work without shifting the open loop gain turnover frequency.......
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