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Old 11th July 2007, 05:22 AM   #1
suzyj is offline suzyj  Australia-Aboriginal
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Default VAS thermal tracking and distortion

Here's a really good example of "the simulations don't tell you everything".

A while ago, I knocked up a pair of MOSFET amps that do 140W into 8 ohms, with lovely low THD (measured 0.0013% at 1KHz). They were based on David Tilbrook's AEM6000 design, which I think is about as good a topology as you'll find for a medium-power MOSFET amp.

I was fairly conservative, and used MJE340/350 transistors for the intermediate stages, similar to Tilbrook's original.

Anyway, I knocked out a 50W (one pair of MOSFETs) version recently. Because the voltages are a little lower, I figured I could use MMBTA06/56 SOT-23 transistors for the second stage. They're faster than the MJE340/350s, and considerably smaller. All good stuff.

Simulations bore my reasoning out. With a little optimisation, I was able to go well under 0.001% THD at 1KHz, 50W into 8 ohms. All good stuff. The power dissipation of all the transistors is well within the limits for the devices.

The schematic I settled on is here.

Next step was to do a layout, get some boards made, and build a couple up to try. I didn't skimp. I used quality MELF resistors, mica and poly capacitors, and a pretty good layout. One of the boards is is shown here.

Anyway, over the last couple of weeks, after a lot of delays due to doing other stuff, I finally fired one up and had a play with it.

The results are nothing short of shocking. Yes, it'll put 50W into 8 ohms, but the THD is around 0.1%. After much hair pulling, I found that the operating conditions were highly dependent on the temperature that these SOT-23 transistors were at. After much stuffing around, I found I could improve the THD to about 0.05% by putting a layer of thermally conductive goo over the whole second stage.

What a mess. Clearly these transistors need to track with one another thermally, or else all the advantages of running a balanced amplifier go totally out the window.

There's nothing that can be done to make this amplifier really useable in its current incarnation. I think I'll chalk this amp up to experience and go back to the drawing board.
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Old 11th July 2007, 06:11 AM   #2
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Default Simulations Don't Agree With Measurements

Several things you might try.

Does your simulator allow you to set different devices at differing temperatures? That may give you some insight into whether the simulations just happened to assume too optimistic PVT conditions. I would also recommend playing with the simulator to see if you can replicate the sensitivity you are seeing in the actual circuit. If you can, then it becomes much easier to examine and test possible mitigation strategies.

A couple of specifics come to mind:

In simulation, check the idle current quiescent points for the VAS and driver stages to make sure that at high voltage swings none of the devices is not near cutoff. In the actual circuit this can be accomplished by varying the idle current.

Consider modifying the VAS stage to a cascode topology. I have found that the VAS stage to be a sensitive part of the amplifier because it must support large voltage swings. A cascode topology will linearize the VAS devices quite nicely.


I am designing an amplifier of a similar topology and found that cascoding the VAS stage yielded >20 dB distortion reduction. You might want to consider that as an option.

Good luck.
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Old 11th July 2007, 07:04 AM   #3
teemuk is offline teemuk  Finland
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Default Re: VAS thermal tracking and distortion

Quote:
Originally posted by suzyj
Clearly these transistors need to track with one another thermally, or else all the advantages of running a balanced amplifier go totally out the window.
I don't intend to sound like a smart-*** but isn't it fairly obvious that a design that relies on using differentials as heavily as your circuit will also need a good balancing for their currents: The VAS might benefit from current mirrors (although they might decrease the ability to swing toward rails). In this kind of design thermal coupling of the differential transistors is understandably very important aspect as well. Maybe you should try to create a layout that allows thermal coupling of devices without using epoxy - that might involve getting rid of some of those SMD parts.
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Old 11th July 2007, 09:56 AM   #4
Bonsai is online now Bonsai  Taiwan
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Looking at the suggestion above, I'd like to shar e my experiences.

I have tried the balanced differential vas with cascode both in simulation (superb results) and in practice (could not measure THD as I don't have the gear yet) on a circuit. If you cascode the differential VAS, you tend to ge t latch-up in most cases with the output swinging either fully high or fully low. This problem cannot be solved with an auto offset control via the input diff amps because the problem is actually in the vas stage and the diff amp(s) cannot influence it - it requires a balancing cct around each differential vas stage. I have not worked that out yet, but looking at Stochino's design, I have a feeling some of the 'glue' transistors he used around his vas are doing this. His topology is different to yours, but the cascode problem is the same. You get the same issue by the way if you use a current mirror load on th e front end diff amp in a balanced (but not differential) topology. Glen Kleinschmidt looked at this one on a post a few months ago, but there is no easy solution.

For your immediate problem, I'd suggest you go for matched integrated devices to improve the situation. For very tight matching you can use the high performance integrated matched npn and matched pnp SO8 pairs (e.g. modern equivalent of MAT01 types) or you might want to try the dual npn and pnp pairs from say NXP. These however are just small signal transistors assembled in the same package - they are not tightly matched but will be off the same wafer and closely located during the assembly process.

The holy grail for the fully balanced topology guys is to have a fully balanced front loaded with current mirrors driving a balanced, cascoded differential VAS. Key to acheiving this is to have the VAS auto balancing when the input signal is 0. I'm working on it!
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Old 11th July 2007, 10:32 AM   #5
Bensen is offline Bensen  Belgium
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Hi suzyj,

I've tried to design an amp using also a bit of the topology of the AEM6000. But I've used one stage less with even more gain than the AEM6000 (if I rememer correctly). I'm also a fan of using symmetrical diff stages.

I put directly a cascoded diff VAS in the design.

http://www.diyaudio.com/forums/attac...amp=1135855644

Fully complementary FET-in FET-out design

Greetz
Ben
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Old 11th July 2007, 10:59 AM   #6
nikwal is offline nikwal  Sweden
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Do you really need that many stages?, why not hook up a input stage with irf9610/610 (or better or course, but you get the general ide)..
Hmm well I got myself a thd instrument recently and I'm happy with the results I got from my amplifier, it was almost the same as in the sim in the simple simulator mode, it can do way more advanced simulations like temperature, worst case and so on..
Otherwise it's similar to the one I'm doing in topology but I'm going with inputstage:irf610/9610, output: irfp240/9140, vas: bd140,139 or similar.. It's not very expensive, I was looking at buying like buz9xx something output transistors, or like the ones you have but I couldnt really get myself to spend that much money on them.. (at least I couldnt find any cheap ones)
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Old 11th July 2007, 12:16 PM   #7
Bonsai is online now Bonsai  Taiwan
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ben,

did you build your circuit and try it out? My VAS was very similar (all bipolar though) and I got the imbalance problem. If you take th e cascode out, the problem is reduced or removed. With single ended differential VAS there is no problem but with a fully balanced design it latches up. You will not see this on a simulation by the way.
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Old 11th July 2007, 12:38 PM   #8
AndrewT is online now AndrewT  Scotland
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Hi,
have you looked at the voltage drop across the collector load resistors (Vr6 & Vr7=45V @ 2.5mA).
Add on the base voltage of the cascode pair and you need at least 59Vdc on the supply to run the cascodes at a tiny Vce=2.6V
Is that what you intended?

I suspect the front is not working and that's where it starts going wrong.

As an aside,
will the Zener on the cascode bases create noise? Will this noise leak into the current getting sent to the second stage?

C4 & C5 should connect to the power ground, not the clean ground.

What stabilises the output offset?
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Old 11th July 2007, 01:12 PM   #9
x-pro is offline x-pro  United Kingdom
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Quote:
Originally posted by AndrewT
Hi,
have you looked at the voltage drop across the collector load resistors (Vr6 & Vr7=45V @ 2.5mA).
Add on the base voltage of the cascode pair and you need at least 59Vdc on the supply to run the cascodes at a tiny Vce=2.6V
Is that what you intended?

I suspect the front is not working and that's where it starts going wrong.

Andrew,

There is nothing wrong with the circuit in this respect - it drops only about 15V across each of R6 and R7.

Cheers

Alex
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Old 11th July 2007, 01:43 PM   #10
AndrewT is online now AndrewT  Scotland
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Hi,
but Q7 &8 ccs is passing ~5mA.
If the LTP is balanced then ~2.5mA goes through each load (R6 & 7 =18k).
That seems more like 45V of drop. Some current may get drawn or injected from the Q11 to 14 bases.
What am I misunderstanding?
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