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Old 22nd June 2007, 07:28 PM   #21
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HI Glen

I agree that it is not possible to use DC coupling without some form of adjustment.

In one bipolar design, I used a compensation transistor to adjust the input bias current and track this with temperature.

THe transistor used in this stage was matched to the input stage transistors (matched triplet).

Slightly easier to design was to use FETs. Again I use closely matched transistors but they still need some fine adjustment.

People have reported thermal oscillation cycles of a few minutes - which I have also observed using TO-92's even tightly coupled thermally. Most people would specify a single package pair now - but maybe two SOT devices stuck together would have much better coupling and faster thermal response... I'll have to give this a try. Not easy because one of the two will be upside down on the other, with its legs in the air...

The bipolar stage with compensation appeared to work better than the FET stage, but I don't have any measurements to report.

cheers
John
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Old 22nd June 2007, 08:01 PM   #22
Don S is offline Don S  United States
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I am new, but if the input was 2 complimentary LTP's I think the DC offset would be greatly reduced. This would be in my thinking because the input bias currents would be close to equal and compliments.
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Old 22nd June 2007, 11:02 PM   #23
Bonsai is offline Bonsai  Taiwan
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I used a complinentary differential diferential input circuit (so 2x NPN and 2 x PNP). I do use a coupling cap in the feedback ntwork (1000F 16V in paallell with 1uF Stacked foil). The offset as measued at the output is 3.7mV. The use of a complimentary pair does reduce offset substantially, and especially so if you use high gain small signal transistors (BC547/557 or 550/560). BTW, I run each side of the pair at 5mA. The overall amp gain is 25x , so if I DC coupled the f/back I would expect <100mV of offset. A simple pot arrangement to null offset (see Amplifier Guru's solution)is fine and drift is minimal, though I don't need to do his on account of the AC coupling.

How the hell did we get here from phase margin improvements arising from a cap on the input side of the diff amp input?
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Old 23rd June 2007, 02:21 AM   #24
pooge is offline pooge  United States
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Quote:
Originally posted by Bonsai


How the hell did we get here from phase margin improvements arising from a cap on the input side of the diff amp input?
My sentiments, exactly. I still don't have a handle on the approach. Since I am not SPICE savvy, I'm still at a loss as to how to go about determining the proper capacitor value. It appears that it needs an optimized value.
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Old 23rd June 2007, 02:42 AM   #25
anatech is offline anatech  Canada
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Hi Don S,
Quote:
I am new, but if the input was 2 complimentary LTP's I think the DC offset would be greatly reduced. This would be in my thinking because the input bias currents would be close to equal and compliments.
Only if all four are matched for beta. This also improves the sound quality. Not my favorite input setup. A single diff pair seems to sound better and you can inject a current into the base to eliminate the DC offset. You can also use an integrator for the same purpose (Duo Beta and other names).

-Chris
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Old 23rd June 2007, 04:26 PM   #26
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Hi pooge

Optimum value mentioned was around 47 pF.
I've concluded this separately, but seems to be about right.

There isn't an easy way of determining this without SPICE unless you hand-calculate something using equivalent circuits (which used to be done).

cheers
John
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Old 23rd June 2007, 05:23 PM   #27
jcx is offline jcx  United States
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From my sim on the previous page I would say that while flat response may be somewhat intellectually attractive in this stage, the “overcompensated” response is quite usable, a few dB loop gain boost above 100 KHz could be welcome

So if you don’t want to measure for an optimum I would recommend just using the max C that gives a sufficiently high low pass corner with the input R, 100-200 KHz is necessary for the single pole response to not impact 20KHz frequency flatness

With very hot diff pair bias, and possibly cascodes it may be a good idea to make this input C a “Zobel” with a 10-100 Ohm in series with the C to add damping
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Old 23rd June 2007, 07:26 PM   #28
pooge is offline pooge  United States
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Thanks. Your sims have two green traces. I assume the lowest green trace is the 1pf trace, and the traces rise with increasing "C". I also assume "overcompensated" means a "C" value greater than 46pf.

Quote:
With very hot diff pair bias, and possibly cascodes it may be a good idea to make this input C a “Zobel” with a 10-100 Ohm in series with the C to add damping
Would the 46pf "optimum" also be optimum with the hot bias or cascode scenario? In other words, is the damping recommended for all hot bias or cascodes, or just for a high "C" way above optimum used for LP filtering?
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Old 23rd June 2007, 07:48 PM   #29
Don S is offline Don S  United States
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So I am lost. Are we saying that there is an input inductance that we are compensating for with C1? Therefore keeping the the input impedance adjusted for frequency? Or does the diff pair preform better with an input impedance dropping with frequency?
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Old 23rd June 2007, 10:00 PM   #30
jcx is offline jcx  United States
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a diff pair can be limited in bandwidth by high source impedance, like volume pots in audio amps

an improvement to provide a low impedance at high frequencies with a C at the +in Q base, this increases the bandwidth of the diff pair for inverting input (feedback) signals which can improve loop stability

the bright green trace at the bottom is indeed the lo C, low bandwidth trace

when I cascode the "optimum" C drops ~1/2? - as the Miller multiplied Q1 Ccb is reduced, but the Q1 base still wants to be ac shorted to ground to maximize feedback input bandwidth

(same pic)
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