estuart said:
Hi Edmond
Please tell me how do you intend to keep the current of Q19/Q22 at exactly 5.1mA ?
It is well known that symetric LTP/mirror designs need some trick to keep next stage at constant idle current with variations of input stage (not seen in ideally equal models in simulators).
I do not see how you've done it in schematic you've attached.
regards
Adam
Bob Cordell said:
Hi Bob,
I have to disagree with you - it is not a matter of a "degree" at all, as we are talking about different effects altogether.
First - the datasheet for ZVN0545A
http://www.zetex.com/3.0/pdf/ZVN0545A.pdf
specifies Vth from minimum of 1V up to maximum of 3V and typical figure may be safely assumed about 2V. Note also that the Vth in the datasheet is measured for Id=1mA and Vds=Vgs. My measurement shows Vth=2V for Id=1mA and that is spot on the datasheet figure.
As you may see from the graph I've posted earlier, the "jump" in capacitance starts exactly at Id=1mA, i.e. on the threshold. It is clearly a threshold-related effect.
Bob Cordell said:
It will move but not much - I can repeat the measurements for 10V and you'll see that. 50 Ohm Rds has not much to do with this effect.
Bob Cordell said:
In my thread I've posted the curve for a "large" MOSFET IRL530N and it also clearly shows that the "jump" effect is taking place in the threshold region with small currents and very obviously far from the "triode" region. I need to repeat the measurements recording the drain current as well just to show you that the "jump" occurs for a very low values of Id. I may even put a device on a heatsink and characterise this effect for a larger range of currents to prove my point.
In this case the device input capacitance not just doubles but could be tripled or quadrupled over the most sensitive area of small currents near the threshold. This "jump" would create an unlinear effect which is not properly reproduced by most simulations and which I did observe previously thought I did not know about it's origins at the time.
It would be very interesting, following Rodolfo's idea, to find a minimum required current for each particular device to stay clear of the "jump" effect. I suspect that for power MOSFETS it could be in the area of few tens to few hundreds of mA, most definetely not few amps, as you've implied. I may consider building a proper jig to test different MOSFETs in this respect.
Alex
estuart said:
G'day Edmond,
Yes I am very interested to see your modified schematic. I've now finalised the design of my 12W amp and am proceeding to build it, but the basic design would be a very good platform for a more serious amp, scaled up for higher power. How about TMC + NDFL + EC + CLASS A ?
Also, sorry for the delay in replying, but I’ve been in the Sin-Bin for the last few days. The stupidity factor of this place has been getting on my goat and I’ve decided that I’ve been wasting far too much valuable time here of late reading through all the threads (a bit of a daft addiction), so I’m giving this place the flick.
So we can continue this discussion via private correspondence, Email your stuff to me at:
glenk@picknowl.com.au
The few other’s here who I’ve had productive, cordial discussions with should know who they are, and are invited to contact me via the email above if interested in the progress of the designs I’ve mooted here.
This is, officially, my last log-in. Cheers + over ‘n’ out,
Glen
darkfenriz said:
Hi Adam,
Of course, the idle current of the two VAS's (29/Q30) in such design would be ill defined without appropriate precautions. However, my design contains a common mode current feedback loop to stabilize each VAS. The current of the top and bottom VAS are sensed by Q27 and Q28 respectively. The sum of these sensing currents (4mA) is subtracted from the current source Q20-R31-Q21, which in turn defines the operating point of Q19 and Q22.
But we are still not done. The bases of Q19 and Q22 need a defined input voltage, you can't just tie them two the floating output of the current mirrors (Q5/6 and Q7/8). Therefor I added R15/R16.
Notice that for best temperature compensation, the voltage drop at R8/R18 should be made equal to the one at R30.
Also notice, that the stability can be improve by providing more common mode feedback. For example, in case of regulated supply lines, we can omit Q17/Q18, D5/D8 and connect R27/R29 (increased to 3k3) directly to these lines.
Admittedly, this design, as my first attempt in this kind, might be further improved. But first, I like to see how other designs (Leach?) behave with respect to this issue. So, would you be so kind to give some links to them?
BTW, I'm a little bit surprised why you didn't ask me some questions about the nested differential feedback loops.
For more on this topic, see:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=96634&perpage=10&highlight=&pagenumber=3 post #29.
Cheers,
Oh, yes. R15/R16 do the job of keeping the next stage current well defined and VAS of course has some local symmetrical feedback loops to satbilise idle current.
I must say this is a really clever approach and in the and very careful and wise schematic.
As far as nested feedback is concerned I am not sure, but it seems that there are three nested loops and the one close to VAS is transitional in respect to pre-drivers and output devices,...
Amen
I got a head ache now
regards
Adam
I must say this is a really clever approach and in the and very careful and wise schematic.
As far as nested feedback is concerned I am not sure, but it seems that there are three nested loops and the one close to VAS is transitional in respect to pre-drivers and output devices,...
Amen
I got a head ache now
regards
Adam
darkfenriz said:
Hi Adam, Thank you.
Actually, there are four nested loops, two NDFL and two Miller.
I'm much obliged to you for your concern about the DC stability. Without it, I'd l probably overlooked the importance of this issue.
Meanwhile, I have made some improvements on this point by increasing the gain (10 times) of the common mode feedback loop by means of two additional current sources (Q17/Q18), see below.
To test the stability, I have doubled the 'size' of Q1 and observed the effect on the standing current of the VAS, which rises by 8.5%.
For comparison, the Leach V4.5, shows an increase of 5.6%, that is, equipped with the same emitter resistors (51R) at the input.
Also, you will see an other trick of mine (I do love tricks of this kind, you know). That's a pot, P1. Why? Let me explain. Years ago (35 or so) I built a pretty nice class-B prototype, THD only 0.01%. After building the final product, the THD was increased to 0.03%. At first I was puzzled, but soon discovered the increase was caused by induction of an asymmetrical lay-out of the power supply leads. Moreover, it was impossible to get the lay-out right.
For once and for all, this should never happen again to me.At the 1ppm THD level, such induced distortion becomes even more apparent, So I decided to include this simple compensating circuitry. Far less expensive, than rewiring an amp, let alone redesigning a faulty PCB!
Cheers, Edmond.
PS: For a more precise compensation, actually, you need two pots.
Soldering this would be much fun! Fault tracing would be an extasy!
I've read about layout distortion in Self's book, he wrote, that taking the feedback point directly from where speaker cable is connceted reduces the effect to nearly nothing, but a pot is still safer.
Still two other output-stage-including loops are taken directly from output, so I must say it is too subtle for me to understand.
Have you ever got similar numbers from some simpler circuits in class AB?
I am currently investigating on if it is possible to get several ppm THD20 from around 10 active devices and simpler solutions and class AB, my simulator says it is doable, but I do not trust software...
I've read about layout distortion in Self's book, he wrote, that taking the feedback point directly from where speaker cable is connceted reduces the effect to nearly nothing, but a pot is still safer.
Still two other output-stage-including loops are taken directly from output, so I must say it is too subtle for me to understand.
Have you ever got similar numbers from some simpler circuits in class AB?
I am currently investigating on if it is possible to get several ppm THD20 from around 10 active devices and simpler solutions and class AB, my simulator says it is doable, but I do not trust software...
x-pro said:
Thanks, Alex.
I'll look forward to the 10V measurements on the ZVN0545A.
Please email me your SPICE model for the ZVN0545A at bob@cordellaudio.com.
I urge you to get an IRFP240 and do the measurements on it, so we are all on the same page, device-wise, and since that is a favorite vertical MOSFET for amplifier builders. They can be had for less than $2.50.
Thanks,
Bob
I knew I had some notes on this subject...
When I was checking out the "P channel mystery" I ran a series
of curves on P and N channel parts.
Relevant to this question, I drove the Gate of an IRFP240, well
heat sinked, at 100 mV rms with a source impedance of 500 ohms
and DC biased with 0 to ~5V Vgs and 0 and +10V Vds, and
swept the frequency while measuring the Gate voltage. The
input capacitance measured would be the sum of Cgs and Cgd.
At 0V Vds, I saw a rolloff corresponding to about 3.7 nF over a
range of 0 to 6V Vgs, with very little variation versus Vds.
AT 10V Vds:
We see 2.2 nF from 0 to 3.5V Vgs (Ids = 10 ma at 3.5V Vgs).
Above 3.5V Vgs and 10 mA Ids the capacitance increases to
2.3 nF at 100 mA, 2.4 nF at 200 mA, 2.8 nF at 500 mA, 2.9 nF
at 1A, and and 3.0 nF at 2A.
At 100 ma Ids and above, we see nonlinearity in the capacitance
which results in a kink in the rolloff curve between 100 KHz
and the rolloff (-3db) point, and remarkably it is similar in
appearance to the kink in the transconductance curve we see
in the P channel parts in the 100 to 1 KHz region in the (IR only)
P channel parts.
I am not seeing the "jump effect" here.
When I was checking out the "P channel mystery" I ran a series
of curves on P and N channel parts.
Relevant to this question, I drove the Gate of an IRFP240, well
heat sinked, at 100 mV rms with a source impedance of 500 ohms
and DC biased with 0 to ~5V Vgs and 0 and +10V Vds, and
swept the frequency while measuring the Gate voltage. The
input capacitance measured would be the sum of Cgs and Cgd.
At 0V Vds, I saw a rolloff corresponding to about 3.7 nF over a
range of 0 to 6V Vgs, with very little variation versus Vds.
AT 10V Vds:
We see 2.2 nF from 0 to 3.5V Vgs (Ids = 10 ma at 3.5V Vgs).
Above 3.5V Vgs and 10 mA Ids the capacitance increases to
2.3 nF at 100 mA, 2.4 nF at 200 mA, 2.8 nF at 500 mA, 2.9 nF
at 1A, and and 3.0 nF at 2A.
At 100 ma Ids and above, we see nonlinearity in the capacitance
which results in a kink in the rolloff curve between 100 KHz
and the rolloff (-3db) point, and remarkably it is similar in
appearance to the kink in the transconductance curve we see
in the P channel parts in the 100 to 1 KHz region in the (IR only)
P channel parts.
I am not seeing the "jump effect" here.
darkfenriz said:
Hi Adam,
No, that's not the kind of distortion I mean, rather: "Distortion number 6: induction distortion", see Douglas Self. Because it's inductive, this type of distortion increases with frequency. Therefor I'm feeding the corrective signal (from the pot) back to a point where the gain also increases with frequency. As the Miller compensation feedback point does have this this property, it is obvious (and easy!) to use it also for error correction of "Distortion number 6". Notice that this whole story does not apply to class-A.
As for your 2nd point, what do you mean by "10 active devices"? If including things like current sources and current mirrors, the answer is no. I think, it's more appropriate to count the number of gain stages. (I don't care how many small signal devices are used, as they are cheap) But I have once designed (and partly built) a fully symmetrical four gain stages amp (input stage, VAS, driver and FET O/P stage). Simulated THD figurers at half power and Iq = 100mA:
200Hz: 0.75 ppm, 1Kc: 1.0 ppm, 2Kc: 1.6 ppm, 20Kc: 15 ppm
If you don't trust you simulator, you could send your schematic to me and we can compare our results.
BTW, I'm not sure how to call a FET output stage with a quiescent of 100mA... 150mA: optimized class-B or class-AB? Mr Cordell, do you have the final answer?
Cheers,
Nelson Pass said:I knew I had some notes on this subject...
At 0V Vds, I saw a rolloff corresponding to about 3.7 nF over a
range of 0 to 6V Vgs, with very little variation versus Vds.
AT 10V Vds:
We see 2.2 nF from 0 to 3.5V Vgs (Ids = 10 ma at 3.5V Vgs).
Above 3.5V Vgs and 10 mA Ids the capacitance increases to
2.3 nF at 100 mA, 2.4 nF at 200 mA, 2.8 nF at 500 mA, 2.9 nF
at 1A, and and 3.0 nF at 2A.
At 100 ma Ids and above, we see nonlinearity in the capacitance
which results in a kink in the rolloff curve between 100 KHz
and the rolloff (-3db) point, and remarkably it is similar in
appearance to the kink in the transconductance curve we see
in the P channel parts in the 100 to 1 KHz region in the (IR only)
P channel parts.
I am not seeing the "jump effect" here.
Nelson, thank you very much for sharing this information as it confirms what I see in my experiments.
I think that you are seeing exactly the same effect as I've described, thought from a slightly different angle. (note - as far as I remember, thought, P-channel IR exgibits the transconductance change v frequency even with a pure voltage drive). You've measured the input capacitance and the change appears in the after threshold region - between 10mA and 500mA Ciss changed by 600pF and from 500mA to 2A there is only 200 pF change.
There is one important note - Ciss consists not just from Ciss=Cgd+Cgs and can not be separated easily into these two. There is a distributed capacitance from the gate to the channel and it is exactly the change of the geometry of the channel that produces the effect of the capacitance increase with drop in the channel resistance. Because this effect is distributed we probably can not talk about only capacitance and the behaviour of the gate is very difficult to describe properly in a few simple equations needed for a simulation model.
Only way I see to find more about, to what capacitance better attribute this change (OK, maybe the "jump" is not the right word
) - Cgs or Cgd, is to measure the Miller effect and see what part of Ciss is needed to account for it. Looking into Faichild paper I've mentioned earlier it appears that the change is mostly NOT to a Miller (i.e. Cgd) capacitance.One more thing - as this effect is distributed and channel resistance dependant, a change in conditions and method of measurement may easily change the result if we try to measure just "capacitance".
I did some more measurements yesterday on IRL530N and will try to post some results later - they looks qute similar to what you've described - Ciss starts to increase with increase in Id just after the threshold and up to a currents of several hundreds of mA. I did measure it for 5 and for 12 V Vds.
I've started this discussion just to show how far from reality most of MOSFET models used for Spice simulations. I think that this point is very clearly proven - no model I know of would behave as a real device in respect of Ciss
. Next step would be to compare different devices in respect of Ciss behavior relevant to conditions found in amplifiers.
Cheers,
Alex
Added some more results here:
http://www.diyaudio.com/forums/showthread.php?s=&postid=1193842#post1193842
Alex
http://www.diyaudio.com/forums/showthread.php?s=&postid=1193842#post1193842
Alex
Nelson Pass said:I knew I had some notes on this subject...
When I was checking out the "P channel mystery" I ran a series
of curves on P and N channel parts.
Relevant to this question, I drove the Gate of an IRFP240, well
heat sinked, at 100 mV rms with a source impedance of 500 ohms
and DC biased with 0 to ~5V Vgs and 0 and +10V Vds, and
swept the frequency while measuring the Gate voltage. The
input capacitance measured would be the sum of Cgs and Cgd.
At 0V Vds, I saw a rolloff corresponding to about 3.7 nF over a
range of 0 to 6V Vgs, with very little variation versus Vds.
AT 10V Vds:
We see 2.2 nF from 0 to 3.5V Vgs (Ids = 10 ma at 3.5V Vgs).
Above 3.5V Vgs and 10 mA Ids the capacitance increases to
2.3 nF at 100 mA, 2.4 nF at 200 mA, 2.8 nF at 500 mA, 2.9 nF
at 1A, and and 3.0 nF at 2A.
At 100 ma Ids and above, we see nonlinearity in the capacitance
which results in a kink in the rolloff curve between 100 KHz
and the rolloff (-3db) point, and remarkably it is similar in
appearance to the kink in the transconductance curve we see
in the P channel parts in the 100 to 1 KHz region in the (IR only)
P channel parts.
I am not seeing the "jump effect" here.
Hi Nelson,
Thanks for digging this out. This is pretty much the exact experiment I had in mind if I had time right now (preparing for he2007).
I assume that in your setup the drain was essentially at an ac ground, so there was no Miller multiplication of Cgd.
Looks like you have confirmed my position by measuring the device at 10 V vds. Up to about threshold you see about 2200 pF.
At 200 mA, it has increased to only 2400 pF, by only about 10%. At this point we are above threshold. At a faily high value of 2A, we are still only up to 3000 pF, a further increase of only 600 pf, or about another 20%. This is a far cry from Alex's claim of a "jump" of a factor of two or more.
The only question left open, in my view, is whether the SPICE model of the IRFP240 reasonably accurately models the increase in capacitance you observed. Alex asserts that the SPICE model does not model this.
Thanks again.
Bob
Hi Bob,
the word "jump" is a purely subjective description and if you and Nelson are unhappy about it I would not use it again
. However it is certainly looks like a very steep curve when there is no drain current present. As you may see from my latest results the capacitance change could be as high as double for lower Vds and it is increasing with current up to it's full value, similar to the value for Vds=0 and drain connected to source. As I've said in my reply to Nelson, the effect is due to the changes in the channel spatial geometry and as such is very difficult to describe in terms of just capacitance as there is obviously some local channel resistance and presence of a "parasitic" JFET is also involved. Because of the complexity of the issue the value of "capacitance" may vary according to the method of measurement, i.e. the frequency used etc.
It would be nice to learn otherwise however it appears that the behaviour of a MOSFET in a linear application is one very hard nut to crack for a SPICE simulator
, and I know at least two areas where models are seriously lacking - one is the modelling of Ciss and it's components Cgs, Cgd and C(gate-channel) behaviour with varying voltages and currents and the second one it the subthreshold drain currents. Second is much easier to fix and most likely is done properly in more complex models, thought I haven't seen these. But the first one may be just impossible to simulate accurately for a proper modelling of the distortion in an amplifier.As I've said earlier my measurements are there only to illustrate the complex nature of MOSFETs, not more than that
Cheers
Alex
x-pro said:
Hi Bob,
the word "jump" is a purely subjective description and if you and Nelson are unhappy about it I would not use it again
As I've said in my reply to Nelson, the effect is due to the changes in the channel spatial geometry and as such is very difficult to describe in terms of just capacitance as there is obviously some local channel resistance and presence of a "parasitic" JFET is also involved. Because of the complexity of the issue the value of "capacitance" may vary according to the method of measurement, i.e. the frequency used etc.
It would be nice to learn otherwise however it appears that the behaviour of a MOSFET in a linear application is one very hard nut to crack for a SPICE simulator
As I've said earlier my measurements are there only to illustrate the complex nature of MOSFETs, not more than that
Cheers
Alex
Hi Alex,
Let's not get side-tracked with semantics. Whether one calls it a jump or not, the change in input capacitance on an IRFP240 is not nearly as much as what you implied it would have been, and not nearly the problem you asserted it to be.
What is the basis of your assertion that SPICE specifically does not model this capacitance correctly (particularly the better LTspice model)? Have you SPICED these parts? Do you have the SPICE model for that Zetex device you measured? If so, please send it to me.
Also, it doesn't look like you have posted the capacitance vs Id for that device at 10 V yet. I'm still looking forward to seeing that plot on the same graph as the one you did at 5V. (I know you did something like that for the larger device, but I would really like to see it for that small Zetex device).
Your assertion that SPICE is way off on this is serious, and you may be right or wrong, but it is important that we know. Yes, MOSFETs are complicated to model, but there are a lot of smart people out there who have been working this issue for many years. So for you to assert that they are way off is something that really needs to be checked out.
Thanks for all your measurement efforts on this. Even if we don't agree, shedding light on an area of controversy always benefits everyone. I don't care whether you are right or wrong about your assertion about the accuracy of SPICE in this area, I just care about what the answer is.
Cheers,
Bob
Hi Bob,
as I've noted earlier, it may be difficult to explain this effect as a purely capacitive, IMHO. And the value may actually depend on the way you measure it. I am thinking about a different way to evaluate that particular unlinearity - better suitable for audio field of applications. It is still a serious problem in my opinion, as it contradicts an intuitive way of looking at the operation of a MOSFET as it introduces a non-Miller increase in Ciss - something almost never mentioned in most appnotes. One noted exception is Ciss(Vgs) curve for some lateral Hitachi FETs - one of these I've quoted in my thread on the input capacitance. It shows very similar character to my results and there is a doubling of Ciss just after the threshold.
http://www.diyaudio.com/forums/showthread.php?postid=1191262#post1191262
Yes, and there is nothing like it in any of the models I've seen. ZVN0545A SPICE model is available here:
http://www.zetex.com/3.0/spice/ZVN0545A.mod
I'll try to find time tomorrow to do 10V curve. I did take some scope curves for ZVN0545A and I attach the picture below with screenshots for 5 and 10V Vds. I will also post screenshots for 0 and 1V Vds in the next message. There is an obvious "kink" in the input voltage of a MOSFET, driven through a resistor, thought for a constant Vds there is no Miller effect.
The rumor has it that there is no adequate MOSFET models for a proper analogue simulation
. I would be happy to be proved wrong on that one.Thank you - same sentiment here.
Regards
Alex