Bob Cordell Interview: BJT vs. MOSFET

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Bob Cordell said:
Hi Jan,
I would have thought that one could accomodate any differences in the tempco of the sensing diode in the details of design of the bias circuit (e.g., vbe multiplier, or whatever).
[snip]Cheers,
Bob


Yes you can but it needs some serious design work I think. The standard app for the ThermalTracks shows 3 pairs of output devices because then you have 6 diodes matching the driver and output Vbe's.

In case of the Sanken's, the diodes are matched to the 4 Vbe's of the two darlingtons, although the absolute value is not matched perfectly and an adjustment pot is needed to set Ibias.

Jan Didden
 
Hi all

I think that trusting a diode to match a Vbe without specifying the current of either is asking for trouble.

One bias circuit which I am increasingly using is the CFP. Here the exact ratio of Vbe's is set by the first stage bias resistor. Then, the actual Vbe of that transistor is set by adjusting the current through it.

I needed this when moving from 2N3055/MJ2955, which were happy with a single transistor stabiliser to MJ15003/4 whose Vbe's were rather different.

Here is one way of implementing it.

cheers
John
 
Bob Cordell said:

Although power MOSFETs are fairly robust devices, they will pop very quickly if their maximum gate-source voltage is exceeded. When parasitic oscillations occur (sometimes at over 100 MHz), the internal voltage swings at the gate can exceed what is at the external terminal of the device, and this is why external gate zeners may not protect a device from failure due to parasitic ocillations.

Bob

Hello Bob,

I was wondering if there was any conceivable way of protecting against this. At this frequency of VHF oscillation. A gate voltage limiter is needed more than a current limiter.

DC overcurrent protection in a regulator might help.

Or does it come down to pure and simply PCB layout and good phase margins in the design ? - (worthwhile regardless)

Triacs and crowbars can react pretty quick.

Best Regards

Kevin
 
Fanuc said:


Hello Bob,

I was wondering if there was any conceivable way of protecting against this. At this frequency of VHF oscillation. A gate voltage limiter is needed more than a current limiter.

DC overcurrent protection in a regulator might help.

Or does it come down to pure and simply PCB layout and good phase margins in the design ? - (worthwhile regardless)

Triacs and crowbars can react pretty quick.

Best Regards

Kevin


As I mentioned, back-to-back 15V gate zeners, for example, will not necessarily protect against this problem. Nor will current limiting in the gate drive circuit (since once a pinhole happens, a heavy current can flow to finish it off from the stored charge on the gate). Bottom line is that the gate-source voltage must never be allowed to exceed +/- 20V under any conditions from any cause. Tight, well-bypassed layouts with suitable gate resistors, and possibly the addition of R-C gate snubber networks, will eliminate the problem of possible VHF parasitic oscillations.

Bob
 
Nelson Pass said:
I don't think this is a practical problem in audio circuits.
In 25 years of using Mosfets I've never seen such parasitics
in anything employing Gate resistance.

:cool:


Hi Nelson,

If you have tight, well-byapassed layouts with 100 ohms or more in gate resistors, you will not likely see this problem. If you want to get more agressive and obtain more of the potential high-frequency capability of the HEXFET by using gate resistors less than 100 ohms, then you may see this problem. Of course, there are undoubtedly people who did not see this problem just because they did not have a fast enough scope. These oscillations can take place between 50 MHz and 200 MHz.

There is a section in my MOSFET power amplifier paper (on my web site at www.cordellaudio.com) where the ways in which these parasitic oscillations can form is described.

What is the lowest value of series gate resistance you have used in any of your common-drain output stage designs?

Bob
 
Re: Parasitic oscillations

estuart said:
Hi Bob,

I’m well aware of the articles on this subject as published in the Siliconix’s ‘Mospower Application Handbook’ as well as your ‘gate snubbers’. Are there any other ‘must have’ papers that could shine more light on this subject?

Cheers,


There likely are, but I can't think of any off the top of my head.

Bob
 
Bob Cordell said:



Hi Nelson,

If you have tight, well-byapassed layouts with 100 ohms or more in gate resistors, you will not likely see this problem. If you want to get more agressive and obtain more of the potential high-frequency capability of the HEXFET by using gate resistors less than 100 ohms, then you may see this problem. Of course, there are undoubtedly people who did not see this problem just because they did not have a fast enough scope. These oscillations can take place between 50 MHz and 200 MHz.

There is a section in my MOSFET power amplifier paper (on my web site at www.cordellaudio.com) where the ways in which these parasitic oscillations can form is described.

What is the lowest value of series gate resistance you have used in any of your common-drain output stage designs?

Bob

Hi Bob,

What about me, with 10 Ohm Rgate and 500Mhz & 1GHz Tek, but i see no parasitic oscillations....

I have seen your paper, its very well illustrated, but one thing confuses me that the paper states the title author as "Robert Cordell" while you are Bob Cordell....whats the secret :)

have a good day
Kanwar
 
Workhorse said:


Hi Bob,

What about me, with 10 Ohm Rgate and 500Mhz & 1GHz Tek, but i see no parasitic oscillations....

I have seen your paper, its very well illustrated, but one thing confuses me that the paper states the title author as "Robert Cordell" while you are Bob Cordell....whats the secret :)

have a good day
Kanwar

Hi Kanwar,

Sounds like you are a very lucky man.

It is very impressive if you are getting away with only a 10-ohm gate resistor on each HEXFET (I assume you are not using laterals) without some other parasitic-oscillation-mitigating condition or circuitry. Are the MOSFETs operated in common drain mode, and fed by emitter follower drivers? Have you blown up any devices at all?

Robert Cordel = Bob Cordell :)

Cheers,
Bob
 
Bob Cordell said:


Hi Kanwar,

Sounds like you are a very lucky man.

It is very impressive if you are getting away with only a 10-ohm gate resistor on each HEXFET (I assume you are not using laterals) without some other parasitic-oscillation-mitigating condition or circuitry. Are the MOSFETs operated in common drain mode, and fed by emitter follower drivers? Have you blown up any devices at all?

Robert Cordel = Bob Cordell :)

Cheers,
Bob

Hi Robert Cordell,

Upper rail mosfets are in CD and lower rail Mosfets are in CS, all N-channel phenomena...Drivers are push-pull types biased at 15mA idle....mosfets are controlled by Transconductance Gain Cell...no mosfets were sacrificed with this type of control...
Hexfets show an extreme variation in their Idrain w.r.t. to variation in VDS with VGS held at constant level....The biggest drawback of Hexfets.....
Here are Id figures obtained with Vgs=3V held constant and VDS is varied from 20V to 220V, device is IRFP264N a 250V 44A HEXFET
Idrain->VDS:
25mA->20V
65mA->50V
155mA->90V
350mA->150V
580mA->200V
650mA->220V
Imagine how Drastic would be the operation of Hexfet amp with +-100VDC rails when subjected to full voltage swing with no load connected conditions....with regular thermally compensated biasing or with your error correction circuitry as well...
Also when subjected to highly reactive loads, their are conditions when Mosfets are Subjected to high VDS , then change in Id would be catastrophic for the device...
But if Transconductance gain Cell is implemented to individual Mosfet then the Biasing wouldnot not change, even if VDS is varied in open load conditions...

Kanwar