Thanks John and Nelson for your answers in post #227 and #228!
Lets continue,
This thread has covered the Cre both in BJT's and FET's a lot but not much mentioned about the base/gate resistor choice which also has an impact of the operation of our SS devices.
I would like to continue develope that subject more as there are maybe more than meets the eyes for many DIY:ers, things like stability, distortion, and of course in conjunction with the Cre.
How do we choose the base/gate resistor value, what criteries and aspects should be taken into consideration in the choice of a proper base/gate resistor?
Could we for instance still do well with a 1k gate resistor into a IRFP240 employed as an output device??
Bob, would you like to start?
Cheers Michael
Lets continue,
This thread has covered the Cre both in BJT's and FET's a lot but not much mentioned about the base/gate resistor choice which also has an impact of the operation of our SS devices.
I would like to continue develope that subject more as there are maybe more than meets the eyes for many DIY:ers, things like stability, distortion, and of course in conjunction with the Cre.
How do we choose the base/gate resistor value, what criteries and aspects should be taken into consideration in the choice of a proper base/gate resistor?
Could we for instance still do well with a 1k gate resistor into a IRFP240 employed as an output device??
Bob, would you like to start?
Cheers Michael
Ultima Thule said:
Empirically select the lowest value that will cure parasitic oscillation with a bit of a safety margin. There is no simple rule for picking the value of gate stopper resistors, other than generally not going more than several hundred ohms – there are too many other factors involved in influencing the susceptibility of an output device to parasitic oscillation.
1k would seriously impact upon the bandwidth and, more importantly, the crossover switching speed in Class AB designs. In fact, if you went through all the trouble of providing a low impedance drive source for the MOSFET’s by means such as a complementary class A emitter follower between the VAS and the output stage, but then needed to add as much a 1k in series with the MOSFET gates to keep oscillations at bay, your efforts would be negated to a large degree.
Cheers,
Glen
Ultima Thule said:
Hi Michael,
This is a good question. The key is to recognize that there are a couple of ways in which an oscillator can be formed in conjunction with resonant circuits involving the gate of the MOSFET. Typically a Colpitts or modified Hartley oscillator can be formed, with stray inductances and the electrode capacitances of the device. This is explained in detail in Section 1.6 of my MOSFET amplifier paper on my web site at www.cordellaudio.com.
For best performance it is desirable to minimize the series gate stopper resistance. Keeping inductance of the gate circuit as small as possible helps, but as described in my amplifier paper, it is also very helpful to put a series R-C network from the gate to ground to further damp the gate node. In my amplifier I am able to use a rather low 47 ohms for the series resistor in combination with a series R-C of 100 ohms and 39 pF to ground.
Cheers,
Bob
CFP output configuration
Gentlemen:
I've been silently following this thread without intervention, for I am not really experienced in the particular subject.
Yet there is a related issue I am very curious to rise and learn what heavyweights have to say.
I am particularly fond of the bjt-mosfet cfp topology as oposed to ef/sf mainstream output stage configuration.
I see at least a couple of interesting properties, namely greater than unity voltage gain and inherent possibiliy of fast local negative feedback.
So far I have been using it in my prototypes without perceived deletrious effects, what makes me wonder why it is not in more widespread use given the fact it makes for a much more relaxed drive burden.
Most certainly my lack of breadth in knowledge regarding scores of past and present desings has to do with this, so the opportunity to gather toghether Cordell, Pass, Curl and others and share their views could be most educational.
Rodolfo
Gentlemen:
I've been silently following this thread without intervention, for I am not really experienced in the particular subject.
Yet there is a related issue I am very curious to rise and learn what heavyweights have to say.
I am particularly fond of the bjt-mosfet cfp topology as oposed to ef/sf mainstream output stage configuration.
I see at least a couple of interesting properties, namely greater than unity voltage gain and inherent possibiliy of fast local negative feedback.
So far I have been using it in my prototypes without perceived deletrious effects, what makes me wonder why it is not in more widespread use given the fact it makes for a much more relaxed drive burden.
Most certainly my lack of breadth in knowledge regarding scores of past and present desings has to do with this, so the opportunity to gather toghether Cordell, Pass, Curl and others and share their views could be most educational.
Rodolfo
Re: CFP output configuration
Rodolfo,
This is a very good question, and I've struggled with it myself. I have never built a CFP output stage, either all bipolar or bipolar-FET, so my actual experience is limited. I can, however, explain a couple of reasons why I have stayed away from it.
First of all, back in the days of quasi-complementary output stages, we essentially used a CFP for the bottom half. In this regard you could say I had some limited experience with them, I suppose. I didn't particularly like them then, but that was mainly because of the asymmetry of the overall output stage that resulted. Stability of the local CFP feedback loop was always a concern, of course.
With regard to crossover distortion, in a complementary CFP output stage you are butting together two quite low-output impedance stages, so the crossover region can in principle have less loss of transconductance as one travels through the region, but the transition from one half of the stage to the other can be more abrupt, so it might lead to higher-order crossover distortion products. If you are dealing with stages with gain greater than unity, their gains must be matched very well top and bottom.
Since the CFP is a local feedback system that must be compensated, it may have a higher-order HF rolloff and contribute more excess phase to the overall open-loop response, and thus the global feedback loop, than an emitter-follower or source follower design.
In most of the CFP topologies I've seen, there is often less effective means for quickly turning off the output transistor by sweeping out minority carrier charge - there is little more than a simple base-emitter resistor; there appears not to be the equivalent of the Locanthi T circuit, which performs much better in this regard. This may be less of a concern if the actual output device is a MOSFET instead of a bipolar, since they are easier to turn off and they have a larger turn-on voltage, on the order of 4V, to work against.
The argument about easing the job of the VAS by incorporating gain into the output stage is a tempting one, but good VAS stages can be made to be very linear, and having gain in the output stage may be just a trade of linearity in the VAS against linearity in the output pair.
In some cases, the CFP's may not clip as nicely.
These are just the kinds of considerations that have kept me away from them, and they may not all be as well-founded as we would like.
I should note that a sort of hybrid of the conventional emitter follower and CFP has been used by Bryston with quite a bit of success.
Bob
ingrast said:
Rodolfo,
This is a very good question, and I've struggled with it myself. I have never built a CFP output stage, either all bipolar or bipolar-FET, so my actual experience is limited. I can, however, explain a couple of reasons why I have stayed away from it.
First of all, back in the days of quasi-complementary output stages, we essentially used a CFP for the bottom half. In this regard you could say I had some limited experience with them, I suppose. I didn't particularly like them then, but that was mainly because of the asymmetry of the overall output stage that resulted. Stability of the local CFP feedback loop was always a concern, of course.
With regard to crossover distortion, in a complementary CFP output stage you are butting together two quite low-output impedance stages, so the crossover region can in principle have less loss of transconductance as one travels through the region, but the transition from one half of the stage to the other can be more abrupt, so it might lead to higher-order crossover distortion products. If you are dealing with stages with gain greater than unity, their gains must be matched very well top and bottom.
Since the CFP is a local feedback system that must be compensated, it may have a higher-order HF rolloff and contribute more excess phase to the overall open-loop response, and thus the global feedback loop, than an emitter-follower or source follower design.
In most of the CFP topologies I've seen, there is often less effective means for quickly turning off the output transistor by sweeping out minority carrier charge - there is little more than a simple base-emitter resistor; there appears not to be the equivalent of the Locanthi T circuit, which performs much better in this regard. This may be less of a concern if the actual output device is a MOSFET instead of a bipolar, since they are easier to turn off and they have a larger turn-on voltage, on the order of 4V, to work against.
The argument about easing the job of the VAS by incorporating gain into the output stage is a tempting one, but good VAS stages can be made to be very linear, and having gain in the output stage may be just a trade of linearity in the VAS against linearity in the output pair.
In some cases, the CFP's may not clip as nicely.
These are just the kinds of considerations that have kept me away from them, and they may not all be as well-founded as we would like.
I should note that a sort of hybrid of the conventional emitter follower and CFP has been used by Bryston with quite a bit of success.
Bob
Re: Re: CFP output configuration
Thanks Bob, makes sense.
In my experience at least, restricted to a single design, this issue is addressed by never turning completely off either half of the output stage. Among the reasons for doing so is bias stabilization (a distinct issue with MOS), gate charge handling (also with MOS), and smooth transition. Active bias control is not very hard and with minor additions eases output protection.
This is a good point, though current devices allow for stable uncompensated cfp stages with bandwidhts in the MHz range whose poles probably get shadowed by foreground dominant pole compensation anyway. Interestingly I use it in a global error correction scheme, where stability could be particularly pesky, and found a simple lead compensation in front tames this safely.
......
This is another goot point, but then I am particularly interested in driving the power stage with an OpAmp or similar low voltage low power stage to exploit off the shelf low cost high performance. This mandates relatively high input impedance and some moderate voltage gain for practical designs in the 50-100W or higher range.
Rodolfo
Thanks Bob, makes sense.
In my experience at least, restricted to a single design, this issue is addressed by never turning completely off either half of the output stage. Among the reasons for doing so is bias stabilization (a distinct issue with MOS), gate charge handling (also with MOS), and smooth transition. Active bias control is not very hard and with minor additions eases output protection.
This is a good point, though current devices allow for stable uncompensated cfp stages with bandwidhts in the MHz range whose poles probably get shadowed by foreground dominant pole compensation anyway. Interestingly I use it in a global error correction scheme, where stability could be particularly pesky, and found a simple lead compensation in front tames this safely.
......
This is another goot point, but then I am particularly interested in driving the power stage with an OpAmp or similar low voltage low power stage to exploit off the shelf low cost high performance. This mandates relatively high input impedance and some moderate voltage gain for practical designs in the 50-100W or higher range.
Rodolfo
Re: Re: CFP output configuration
I’ve used complementary unity voltage gain CF BJT-BJT pairs for output stages many times with great success. Over the standard Darlington emitter follower, a properly implemented unity gain configured CFP offers greater bandwidth, significantly improved linearity (that will stomp any MOSFET) and less crossover distortion. They are particularly good for Class A stages, where the best linearity is sought. Turn off of the output devices generally isn’t a problem, as low value (22-100 ohm) resistors can be used across the BE junction of each output device (22 ohms only sets the quiescent current of the driver transistor to approx 30mA) No localised frequency compensation is required – a base stoper of 47 or 100 ohms for the driver transistor and care taken in layout has always worked for me (even with high fT devices). A set of complementary unity gain CFP’s are also much easier to temperature stabilise, as the VBE multiplier only has to compensate for the BE junction variations of the driver transistors, not the output devices. The driver transistors can usually be conveniently mounted along with the VBE multiplier transistor on a separate heatsink from the output devices, which doesn't get nearly as hot or suffer the same fluctuations in temperature.
There have been lots of derivations of the CFP configuration in attempts to achieve extra voltage gain in the output stage, but I’ve never been tempted to even bother with such arrangements. They almost always complicate the quiescent current temperature stability of the output stage and the closed loop stability of the amplifier. There are much better ways of increasing the open loop gain of an amplifier.
For those who are wondering what I mean by complementary unity voltage gain CF BJT-BJT pairs, it is as shown here:
http://www.dself.dsl.pipex.com/ampins/dipa/dpafig1.gif
Cheers,
Glen
Bob Cordell said:
I’ve used complementary unity voltage gain CF BJT-BJT pairs for output stages many times with great success. Over the standard Darlington emitter follower, a properly implemented unity gain configured CFP offers greater bandwidth, significantly improved linearity (that will stomp any MOSFET) and less crossover distortion. They are particularly good for Class A stages, where the best linearity is sought. Turn off of the output devices generally isn’t a problem, as low value (22-100 ohm) resistors can be used across the BE junction of each output device (22 ohms only sets the quiescent current of the driver transistor to approx 30mA) No localised frequency compensation is required – a base stoper of 47 or 100 ohms for the driver transistor and care taken in layout has always worked for me (even with high fT devices). A set of complementary unity gain CFP’s are also much easier to temperature stabilise, as the VBE multiplier only has to compensate for the BE junction variations of the driver transistors, not the output devices. The driver transistors can usually be conveniently mounted along with the VBE multiplier transistor on a separate heatsink from the output devices, which doesn't get nearly as hot or suffer the same fluctuations in temperature.
There have been lots of derivations of the CFP configuration in attempts to achieve extra voltage gain in the output stage, but I’ve never been tempted to even bother with such arrangements. They almost always complicate the quiescent current temperature stability of the output stage and the closed loop stability of the amplifier. There are much better ways of increasing the open loop gain of an amplifier.
For those who are wondering what I mean by complementary unity voltage gain CF BJT-BJT pairs, it is as shown here:
http://www.dself.dsl.pipex.com/ampins/dipa/dpafig1.gif
Cheers,
Glen
Re: Re: CFP output configuration
Jan, I posted earlier a link to the "Ever made a MOSFET CFP ..." thread, here it is
Rodolfo
janneman said:
Jan, I posted earlier a link to the "Ever made a MOSFET CFP ..." thread, here it is
Rodolfo
Here are a couple of additional things to keep in mind with CFP output stages.
First, on the plus side, they will tend to have better thermal bias stability, since it is the Vbe of the driver transistor that is more in control of bias, and it is subject to much less heating and temperature variation as a function of program material.
In a conventional CFP, the collector-base (or drain-gate) capacitance plays a major role in the frequency compensation of the stage. Unfortuanately, this capacitance can be large and highly non-linear, so the compensation frequency will move around with signal swing, causing HF distortion. In a sense, this capacitance is subject to the usual Miller effect multiplication, whereas it is not multiplied in an emitter follower or source follower output stage.
I would also guess that the output inductance of a CFP is higher than that of a follower, since it will begin to go inductive at the local loop's gain crossover frequency.
In some cases the compensation of the CFP will be somewhat affected by the load impedance being driven as well. All of these considerations will vary with the particulars of the implementation.
It is probably also important to distinguish between CFP output stages with gain and those without. For unity gain CFP stages, the driver can get into saturation as it pulls down on the base or gate while the output is rising. This may prevent the output from getting as close to the rail as would be the case for a follower output stage that uses a boosted supply. This effect will be even greater if the output device being used is a MOSFET, with its higher turn-on voltage requirement. If, for example, the MOSFET needs 6V of forward gate voltage for a high-current turn-on, and the driving stage needs 1 V of headroom to work, you may only be able to get within 7 volts of the rail in a unity gain CFP using a MOSFET output transistor.
The situation is different for a CFP with gain. In this case, the driver is less likely to run out of headroom and saturate, and you can get much closer to the rails at the output. However, it is then easier to saturate the output transistor, and this is especially bad if a bipolar is being used as the output transistor.
Again, I have not had much direct experience with CFPs, so these are just things to keep in mind and judge for yourself. Doing some SPICE runs on CFP vs follower output stages should be very revealing of the degree of any of these effects.
Bob
First, on the plus side, they will tend to have better thermal bias stability, since it is the Vbe of the driver transistor that is more in control of bias, and it is subject to much less heating and temperature variation as a function of program material.
In a conventional CFP, the collector-base (or drain-gate) capacitance plays a major role in the frequency compensation of the stage. Unfortuanately, this capacitance can be large and highly non-linear, so the compensation frequency will move around with signal swing, causing HF distortion. In a sense, this capacitance is subject to the usual Miller effect multiplication, whereas it is not multiplied in an emitter follower or source follower output stage.
I would also guess that the output inductance of a CFP is higher than that of a follower, since it will begin to go inductive at the local loop's gain crossover frequency.
In some cases the compensation of the CFP will be somewhat affected by the load impedance being driven as well. All of these considerations will vary with the particulars of the implementation.
It is probably also important to distinguish between CFP output stages with gain and those without. For unity gain CFP stages, the driver can get into saturation as it pulls down on the base or gate while the output is rising. This may prevent the output from getting as close to the rail as would be the case for a follower output stage that uses a boosted supply. This effect will be even greater if the output device being used is a MOSFET, with its higher turn-on voltage requirement. If, for example, the MOSFET needs 6V of forward gate voltage for a high-current turn-on, and the driving stage needs 1 V of headroom to work, you may only be able to get within 7 volts of the rail in a unity gain CFP using a MOSFET output transistor.
The situation is different for a CFP with gain. In this case, the driver is less likely to run out of headroom and saturate, and you can get much closer to the rails at the output. However, it is then easier to saturate the output transistor, and this is especially bad if a bipolar is being used as the output transistor.
Again, I have not had much direct experience with CFPs, so these are just things to keep in mind and judge for yourself. Doing some SPICE runs on CFP vs follower output stages should be very revealing of the degree of any of these effects.
Bob
Right. In BJT-BJT CFP, the driver almost always work in saturation mode (very low Vce), during large signals.
From engineering POV offcourse this is bad, but something is interesting. The consumer (audience who doesn't know electronics) likes the sound of this typical CFP sound (driver saturated). They said it has more "spirit" in the sound reproduction.
ingrast said:
Yes, exactly. Tradeoffs is what engineering is all about.
I have often asserted the following theory about what affects an engineer's design choices: The choices an engineer makes are most strongly governed by what he fears and tries to avoid.
Many of the engineers I have worked with over the years agree with this observation. Different engineers fear different things to different degrees, and have different comfort levels with different approaches and technologies. Sometimes this is historical, based on past experience. This explains why two equally smart and informed engineers can solve a problem in two very different ways and wind up with often similarly good end results.
Bob
Bob Cordell said:
My experience is different: most often engineers I worked with were driven by what they love more. And sometimes this love was based on strange things, such as names of schematical solutions, shape of them, cases in life hapenned when they used some particular solutions...
lumanauw said:
Right. In BJT-BJT CFP, the driver almost always work in saturation mode (very low Vce), during large signals.
From engineering POV offcourse this is bad, but something is interesting. The consumer (audience who doesn't know electronics) likes the sound of this typical CFP sound (driver saturated). They said it has more "spirit" in the sound reproduction.
Exactly the same is true for the driver transistor in a BJT-BJT Darlington configured pair. From an engineering POV this is hardly a problem, as BJT's generally dont mind working at low collector-emitter voltages. Also, the driver only truely enters saturation during clipping, not during normal linear amplification.
There is also no significant difference in the obtainable output swing of a unity gain BJT-BJT CFP over a Darlington BJT-BJT pair.
For a Darlington pair the maximum obtainable output swing (with the base of the driver transistor driven beyond the rail) is equal to the saturation voltage of the driver transistor plus the BE voltage of the output transistor plus the voltage drop across the emitter ballast resistor.
With the unity gain CFP it is also equal to the saturation voltage of the driver transistor plus the BE voltage of the output transistor plus the voltage drop across the emitter ballast resistor, but with the exception that the base of the driver transistor does not need to be driven beyond the rail voltage.
A simplified scribble to demonstrate:
An externally hosted image should be here but it was not working when we last tested it.
Cheers,
Glen