Tim__x said:Bob's formula is simple enough to understand that it doesn't really need a drawn out explanation, but here goes.
If a 1K increase produces an increase in power dissipation such that the die temperature increases by more than 1 additional kelvin the local thermal system will enter thermal runaway.
Tim, thanks for bringing me up to speed on this. Most of this makes sense to me, but there are still two things that I'm not really following:
a) First of all, this equation completely ignores the thermal feedback loop provided by the bias circuit (typically a Vbe multiplier). So it assumes that something is going to happen so quickly that the bias circuit won't have time to respond.
In my view, this is an oversimplification. The transistor is relatively tightly coupled to the thermal mass of the heatsink. So it is difficult for the die temperature to change *that* quickly.
b) I don't see why the magic number of Beta is 1. To me it seems that the magic number is zero. Positive values mean that the system could enter thermal runaway IF the bias system doesn't have good thermal feedback. Negative values mean there is no problem.
But to assert that a positive value of 0.5 is borderline dangerous and a positive value of 1 is the absolute maximum stable number makes no sense to me.
Instead, the entire system (including the bias circuit) MUST have a negative value to be stable. There are many, many time constants in the system, both in the forward direction and the reverse direction. I would agree that a lower value of Beta would lead to less overshoot. It would also allow for a longer time lag before the bias circuit reacts without endangering the amplifier.
But since so many critical aspects are completely ignored by this equation, I think its usefulness is quite limited.
A question on Lateral's mosfets
Hello,
Was wondering if anyone has tried using RC filter over the gates of Lateral mosfets (much like Bob did with his error correction amp). I have seen values as low as 100r but the N chl one in particular is prone to oscillate.
Another question regarding using small caps over the N Chl or P chl lateral's is to equalise the Input capacitance.
Have seen different resistors being used on the Gates (to adjust the bandwidth) but I suspect the positive and negative slew rate of the output stage will be quite different. This is quite apart from the VAS/miller type slewing from Doug Self's book.
Or is the best way just buffering ?
I have seen some designs (I think it was Erno Borberly) where caps are connected between the gate and the drain of the N Chl. in an attempt to equal the capacitances. You then have to take account of the bootstrapping affect of the transconductance in source follower mode on the various capacitances. Something Borberly obviously never done right if you read Bob's mosfet error amplifer paper.
Any tips on sizes of ferrite beads also. May try this also.
All the best
Kevin
Hello,
Was wondering if anyone has tried using RC filter over the gates of Lateral mosfets (much like Bob did with his error correction amp). I have seen values as low as 100r but the N chl one in particular is prone to oscillate.
Another question regarding using small caps over the N Chl or P chl lateral's is to equalise the Input capacitance.
Have seen different resistors being used on the Gates (to adjust the bandwidth) but I suspect the positive and negative slew rate of the output stage will be quite different. This is quite apart from the VAS/miller type slewing from Doug Self's book.
Or is the best way just buffering ?
I have seen some designs (I think it was Erno Borberly) where caps are connected between the gate and the drain of the N Chl. in an attempt to equal the capacitances. You then have to take account of the bootstrapping affect of the transconductance in source follower mode on the various capacitances. Something Borberly obviously never done right if you read Bob's mosfet error amplifer paper.
Any tips on sizes of ferrite beads also. May try this also.
All the best
Kevin
Charles Hansen said:
Hi Charles,
Most of your observations are right on target, and it is certainly fair to say that this equation is a simplification. As with any simple equation, there are some ways in which it may be biased toward the worst case, and others in which it doesn't cover some other worst case situations. As such, it is still very useful as a guide, but of course your mileage may vary.
The most important thing that it does is to isolate the local thermal feedback issue - the one that does not involve the heat sink. You are absolutely correct that it ignores the heatsink AND ignores the negative thermal feedback provided by the tracking (or mis-tracking) Vbe multiplier. That is intentional. Those are long-term effects that do not have time to come into play when a local thermal runaway occurs. Yes, they of course do provide negative thermal feedback, but only on a long-term basis.
You are also absolutely right that there are multiple different time constants at work here. The three most obvious are the thermal time constants of the die, the package and the heat sink. These are separated by orders of magnitude. The heat sink time constant is much, much longer than the first two, and that is why this equation makes sense to use.
Thermal runaway can happen in the blink of an eye, much faster than the heat sink can react. That is the problem, and that is why this equation is very useful. It sets a limit on what you can get away with.
Indeed, the diligent designer who uses a huge heat sink with a very large thermal mass will be MORE governed by this equation. I realize that this may at times be non-intuitive. Viewing the heat sink temperature as not moving during the timeframe of a local thermal runaway biases the equation toward the worst case, and this is what we want.
But it is also true that there can be situations that make things even worse. For example, under signal conditions when the output stage is driving a load, the gm of the device under consideration may likely increase, increasing thermal Beta. I don't know whether the 25 ms half-cycle time of a 20 Hz bass note would be enough time for thermal runaway to get started and persist, of course (that same transistor will be given some relief when it turns off on the next half cycle).
The reason why thermal Beta = 1 is so important is simply from feedback theory. When positive feedback loop gain = 1, closed loop gain goes to infinity and we have runaway. The thermal equivalent of latch-up.
The arbitrary value of a positive feedback factor of 0.5 is a reasonable threshold for serious concern because that is where the closed loop gain of the thermal system is 2. At this point, all thermal changes and disturbances are multiplied in magnitude by a factor of two.
Your use of the ThermalTrak transistors largely immunizes you from the issues that this equation deals with, and that is the beauty of them.
Cheers,
Bob
Hi Kevin,
These are questions I'm also quite curious about.
The recent National AppNote 1645 for the LM4702 reads on series R's that the optimum values are determined empirically for given actual parts by overdriving them and adjust for clean slewing while maintaining stability (which is also adressed there with an output Zobel). Rising and falling slewrates don't seem to be matched on the scope shots printed. Maybe with series R//ferrite bead might be a way to get more symmetric slewing.
I would also think a parallel cap across the gate might be good from a standpoint of stable conditions for a buffer stage ahead (more known and more stable capacitance, thus easier to compensate for if the buffer stage itself is a feed-back design).
AppNote 104 from Linear holds an example for an op-amp closed loop around a FET to create a precision current sink (btw, an example for local device linearisation which I now mentioned twice in the starving feeback thread, no response so far... hhm, did I write totally silly things there?). There they use this series R//ferrite bead and also a snubber R+C across the gate for stabilisation/compensation. I've used similar circuits for electronic ballasts with success (after a lot of trimming, though).
Regards, Klaus
These are questions I'm also quite curious about.
The recent National AppNote 1645 for the LM4702 reads on series R's that the optimum values are determined empirically for given actual parts by overdriving them and adjust for clean slewing while maintaining stability (which is also adressed there with an output Zobel). Rising and falling slewrates don't seem to be matched on the scope shots printed. Maybe with series R//ferrite bead might be a way to get more symmetric slewing.
I would also think a parallel cap across the gate might be good from a standpoint of stable conditions for a buffer stage ahead (more known and more stable capacitance, thus easier to compensate for if the buffer stage itself is a feed-back design).
AppNote 104 from Linear holds an example for an op-amp closed loop around a FET to create a precision current sink (btw, an example for local device linearisation which I now mentioned twice in the starving feeback thread, no response so far... hhm, did I write totally silly things there?). There they use this series R//ferrite bead and also a snubber R+C across the gate for stabilisation/compensation. I've used similar circuits for electronic ballasts with success (after a lot of trimming, though).
Regards, Klaus
Bob Cordell said:
I'm not sure I agree with you. If this were true, all of the solid-state amps that have been built for the last 45 years would be self-destructing at an alarming rate. But in the real world, I just don't see that many amps blowing up from this problem.
Bob Cordell said:
But your equation doesn't give a gain of 1. When the Beta you defined is 1, then the gain is actually 2. The formula says that when the temperature goes up 1 degree (for whatever reason) that the temperature coefficient is such that you will see the temperature rise ANOTHER degree. That is a gain of 2, not 1.
When your formula gives a Beta of ZERO, then the gain is 1 (at least to my way of thinking).
Bob Cordell said:
And we've built thousands of BJT amplifiers WITHOUT ThermalTrak without any problems as well.
I re-read your original AES paper on the error-correction amplifier. I liked your curves showing the improved bias stability of the MOSFET amps over the BJT amps. There are a lot of variables involved, and maybe too many to say for sure what is happening there.
But if I understand you correctly, one of the main things that makes the vertical parts better in this regard than the BJT's is the fact that gm is so much lower. This is easily addressed by increasing the value of the emitter resistor on the BJT to a couple of ohms. Then the gm would be comparable. But I don't think this would really result in a better amp.
And again, for the best performance in this parameter, look no further than the lateral parts. The zero tempco occurs when the Vgs threshold decrease is offset by the channel resistance increase. These effects both occur within the die itself, so there is essentially no lag involved. Now you can have your cake and eat it too. It would be like having a ThermalTrak BJT with the entire bias circuit on the die with the output device, and no lag whatsoever.
But having built amps with all three types of output devices, I don't think that this parameter is of such overriding importance that it outweighs many other considerations. YMMV.
hitsware said:
Bart Locanthi developed this circuit for JBL in 1966. It was the first fully complementary amplifier (as far as I know). It was described in two articles. One is the July 1967 AES Journal (available as a download from the AES website, but for a fee), and the other was for Electronics World. Marshall Leach has kindly made this article available for a free download at:
http://users.ece.gatech.edu/~mleach/papers/tcir/tcir.pdf
From the original AES paper, Mr. Locanthi wrote:
"the Locanthi three-stage cascaded complementary symmetry emitter-follower output circuit, hereafter referred to as the T-circuit. (Because of its PNP-NPN symmetry, the configuration has a general appearance of a bridged-T circuit.)"
Locanthi was a true genius, making many contributions to audio, both in the field of electronics and loudspeakers. In addition to the T-circuit (which is still the best output stage extant, IMO), he invented (or perfected, I forget which) "Dynamical Analogies" which allows analyzing the mechanical components of a loudspeaker as an electical network of L, C, and R.
Re: A question on Lateral's mosfets
Lateral devices (and verticals too, for that matter) need a series gate resistor to keep from oscillating. When used as a follower, you can use values as high as several kohms without limiting the bandwidth. The input capacitance is essentially just Cgd, as Cgs is bootstrapped out of the picture. Most spec sheets specifiy Cgd and Cin, where Cin = Cgs + Cgd.
You also need to have a local bypass cap on the rail. This should be a 1000 pF or so from the drain (assuming a source follower output) to the heatsink, which is typically the closest nearby ground.
This seems good on paper, but sucks in real life. The best sounding cap is no cap.
Why?
No need. You can easily get over 100 kHz bandwidth from a reasonably low output impedance voltage gain stage.
Yes, an embarrassing gaffe. He never bothered to correct himself on this point to the best of my knowledge.
Yes, zero uH. Ferrite sucks, from a sonic perspective. (Do a search under posts by my name to read more.)
Fanuc said:
Lateral devices (and verticals too, for that matter) need a series gate resistor to keep from oscillating. When used as a follower, you can use values as high as several kohms without limiting the bandwidth. The input capacitance is essentially just Cgd, as Cgs is bootstrapped out of the picture. Most spec sheets specifiy Cgd and Cin, where Cin = Cgs + Cgd.
You also need to have a local bypass cap on the rail. This should be a 1000 pF or so from the drain (assuming a source follower output) to the heatsink, which is typically the closest nearby ground.
Fanuc said:
This seems good on paper, but sucks in real life. The best sounding cap is no cap.
Fanuc said:
Why?
Fanuc said:
No need. You can easily get over 100 kHz bandwidth from a reasonably low output impedance voltage gain stage.
Fanuc said:
Yes, an embarrassing gaffe. He never bothered to correct himself on this point to the best of my knowledge.
Fanuc said:
Yes, zero uH. Ferrite sucks, from a sonic perspective. (Do a search under posts by my name to read more.)
Re: Re: A question on Lateral's mosfets
Hi Charles,
You're thinking zero feedback amps here. Bob's (feedback) amp has a unity loop gain frequency of around 2 MHz, so the phase lag of the output stage needs to be low at that freq. That's whey he uses the gate network in his article. The series R-C to ground from the gate minimizes the series R needed, by reducing the maximum negative real part of the input impedance.
Edit: Keeping the series gate resistor small also allows the error correction to do its thing better at high frequencies, so less compensation is needed in the EC loop.
Charles Hansen said:
Hi Charles,
You're thinking zero feedback amps here
. Bob's (feedback) amp has a unity loop gain frequency of around 2 MHz, so the phase lag of the output stage needs to be low at that freq. That's whey he uses the gate network in his article. The series R-C to ground from the gate minimizes the series R needed, by reducing the maximum negative real part of the input impedance.Edit: Keeping the series gate resistor small also allows the error correction to do its thing better at high frequencies, so less compensation is needed in the EC loop.
Re: Re: Re: A question on Lateral's mosfets
Hello Andy,
This was my thinking on using RC filters etc like Bob has done and for them reasons - for a error correction amp!. I have loads of lateral 2SK135/2SJ50 etc and some Magnatec's available and might as well use them!
Might modify a Tandberg design though as Bob's loop stability in the EC loop is for Vertical mosfets.
Charles,
I was thinking of driving lots of Fets in a output stage and the drive currents are going to be a lot different for each side. I disagree about the best cap being no cap - some are better/more linear than the caps in semiconductors! same with your dismissal with ferrite beads!
I think it's interrelated with the point above about different Zin's and Fet capacitances and different drive currents from the VAS etc - if feed directly.
Klaus,
I will have alook at your suggested App Notes tomorrow. Thanks for the links.
Regards
Kevin
andy_c said:
Hi Charles,
You're thinking zero feedback amps here
Edit: Keeping the series gate resistor small also allows the error correction to do its thing better at high frequencies, so less compensation is needed in the EC loop.
Hello Andy,
This was my thinking on using RC filters etc like Bob has done and for them reasons - for a error correction amp!. I have loads of lateral 2SK135/2SJ50 etc and some Magnatec's available and might as well use them!
Might modify a Tandberg design though as Bob's loop stability in the EC loop is for Vertical mosfets.
Charles,
I was thinking of driving lots of Fets in a output stage and the drive currents are going to be a lot different for each side. I disagree about the best cap being no cap - some are better/more linear than the caps in semiconductors! same with your dismissal with ferrite beads!
I think it's interrelated with the point above about different Zin's and Fet capacitances and different drive currents from the VAS etc - if feed directly.
Klaus,
I will have alook at your suggested App Notes tomorrow. Thanks for the links.
Regards
Kevin
Re: Re: Re: A question on Lateral's mosfets
Of course. And you're not? I'm shocked -- shocked!!
Yahbut, Bob's amp was using vertical devices which have an order or two higher Cgd than lateral devices (which is what the OP was asking about).
For example, the Cgd of an N-channel lateral part is only 10 pF. So even if you used a 5 kohm series gate resistor, you are still looking at a -3 dB point of around 3.5 MHz...
I'm not saying you necessarily would want to do that, but it probably wouldn't wreck everything to do so.
Edit: I looked at Bob's circuit. Don't forget those nice Zener diodes he has protecting the gates. Take a look at Figure 7 of the following 500 mW Zener diode data sheet:
http://www.onsemi.com/pub/Collateral/MMSZ2V4T1-D.PDF
Depending on the bias voltage, those diodes are adding another 50 or 100 pF of capacitance to ground, in addition to the explicit caps he has drawn in the circuit.
andy_c said:You're thinking zero feedback amps here
Of course. And you're not? I'm shocked -- shocked!!
andy_c said:
Yahbut, Bob's amp was using vertical devices which have an order or two higher Cgd than lateral devices (which is what the OP was asking about).
For example, the Cgd of an N-channel lateral part is only 10 pF. So even if you used a 5 kohm series gate resistor, you are still looking at a -3 dB point of around 3.5 MHz...
I'm not saying you necessarily would want to do that, but it probably wouldn't wreck everything to do so.
Edit: I looked at Bob's circuit. Don't forget those nice Zener diodes he has protecting the gates. Take a look at Figure 7 of the following 500 mW Zener diode data sheet:
http://www.onsemi.com/pub/Collateral/MMSZ2V4T1-D.PDF
Depending on the bias voltage, those diodes are adding another 50 or 100 pF of capacitance to ground, in addition to the explicit caps he has drawn in the circuit.
Re: Re: Re: Re: A question on Lateral's mosfets
I don't get it. You asked a question, presumably because you didn't know the answer. I have tried those exact experiments you were asking about and gave you the results of careful listening tests (for free, no less!). Then you want to argue with me about it, even though you apparently have no experience with the subject.
I don't get it.
Like Rafiki told Simba in The Lion King, "look harder!"
Fanuc said:
I don't get it. You asked a question, presumably because you didn't know the answer. I have tried those exact experiments you were asking about and gave you the results of careful listening tests (for free, no less!). Then you want to argue with me about it, even though you apparently have no experience with the subject.
I don't get it.
Fanuc said:
Like Rafiki told Simba in The Lion King, "look harder!"
Re: Re: Re: Re: A question on Lateral's mosfets
(Hal 9000 voice: )
Hello Charles,
Looking at apples to apples for complementary parts, I get
between 2 and 3 times the Cdg. And you have not mentioned
the higher Cgs of the laterals, which coupled with the lower
transconductance becomes another source of bandwidth loss.
I have no issue with the performance of Laterals, and $3 is
certainly not too much money for the parts, but I feel that the
Verticals offer better performance through the bass and midrange
due to the much higher transconductance. I have never found
thermal tracking or reliability to be an issue, but as you know,
I like to use lots of parts and big sinks, and I bias very high.
Charles Hansen said:
(Hal 9000 voice: )
Hello Charles,
Looking at apples to apples for complementary parts, I get
between 2 and 3 times the Cdg. And you have not mentioned
the higher Cgs of the laterals, which coupled with the lower
transconductance becomes another source of bandwidth loss.
I have no issue with the performance of Laterals, and $3 is
certainly not too much money for the parts, but I feel that the
Verticals offer better performance through the bass and midrange
due to the much higher transconductance. I have never found
thermal tracking or reliability to be an issue, but as you know,
I like to use lots of parts and big sinks, and I bias very high.
Re: Re: Re: A question on Lateral's mosfets
Hi Andy. Thanks for explaining this. You are exactly right. The use of the R-C effectively damps the resonance that can lead to parasitic oscillation, allowing one to use a smaller series gate resistance and get more net bandwidth at the output stage. This may not be intuitively obvious to some, who might think that the added capacitance in the R-C leg cancels out the advantage of the lower allowed gate series resistance, but it beomes more clear when one looks at the numbers and sees how small the value is of the added capacitance to make this work.
Cheers,
Bob
andy_c said:
Hi Charles,
You're thinking zero feedback amps here
Edit: Keeping the series gate resistor small also allows the error correction to do its thing better at high frequencies, so less compensation is needed in the EC loop.
Hi Andy. Thanks for explaining this. You are exactly right. The use of the R-C effectively damps the resonance that can lead to parasitic oscillation, allowing one to use a smaller series gate resistance and get more net bandwidth at the output stage. This may not be intuitively obvious to some, who might think that the added capacitance in the R-C leg cancels out the advantage of the lower allowed gate series resistance, but it beomes more clear when one looks at the numbers and sees how small the value is of the added capacitance to make this work.
Cheers,
Bob
Thermal Bias Instability
Hi Charles,
I mis-spoke a bit yesterday when I said that the use of ThermalTrak transistors gets you away from the local positive thermal feedback concern that is addressed by my equation.
The situation isn't always quite that rosy. Depending on the particular ThermalTrak bias scheme used, not all of the ThermalTrak transistors' diodes will play a full role in the Vbe multiplier. For example, let's say you build a big single-ended amplifier with eight ThermalTrak output pairs, 90V rails, and bias each transistor at 150 mA with 0.1 ohm resistors. How are you going to use all of those 16 ThermalTrak diodes, much less in a way such that each diode individually tends to the bias of its associated BJT?
In typical output stages, all of the NPN transistors will get the same base voltage via the drivers from the bias spreader. This means that, even with ThermalTrak transistors, current hogging among the eight output NPN's (for example) will still be governed by the equation I showed.
It is also notable that in a conventional non-thermalTrak output stage that some of the transistors in a large amplifier like the one I described above will be of necessity physically far away from the bias spreader transistor that is bolted to the heat sink. Their behavior will especially be influenced by the large thermal lag of the heatsink.
Anyway, the bottom line here is that the ThermalTrak transistors are wonderful, but they don't completely eliminate some aspects of local thermal positive feeback.
Cheers,
Bob
Hi Charles,
I mis-spoke a bit yesterday when I said that the use of ThermalTrak transistors gets you away from the local positive thermal feedback concern that is addressed by my equation.
The situation isn't always quite that rosy. Depending on the particular ThermalTrak bias scheme used, not all of the ThermalTrak transistors' diodes will play a full role in the Vbe multiplier. For example, let's say you build a big single-ended amplifier with eight ThermalTrak output pairs, 90V rails, and bias each transistor at 150 mA with 0.1 ohm resistors. How are you going to use all of those 16 ThermalTrak diodes, much less in a way such that each diode individually tends to the bias of its associated BJT?
In typical output stages, all of the NPN transistors will get the same base voltage via the drivers from the bias spreader. This means that, even with ThermalTrak transistors, current hogging among the eight output NPN's (for example) will still be governed by the equation I showed.
It is also notable that in a conventional non-thermalTrak output stage that some of the transistors in a large amplifier like the one I described above will be of necessity physically far away from the bias spreader transistor that is bolted to the heat sink. Their behavior will especially be influenced by the large thermal lag of the heatsink.
Anyway, the bottom line here is that the ThermalTrak transistors are wonderful, but they don't completely eliminate some aspects of local thermal positive feeback.
Cheers,
Bob