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Old 15th March 2013, 04:32 PM   #381
pidigi is offline pidigi  Italy
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Quote:
Originally Posted by gk7 View Post
5.6mA seems rather low to me, this is 1/3 of the "V" parts I use. I would not
cheap out on these parts and order them form Spencer ("BL" grade), as long as
he still has 2SJ74 available, and ask for the highest Idss matched quads he
can offer (should be around 10mA or so).
thank you Georg, I will follow your suggestion

Quote:
I can confirm that the "-4dB" setting (this is 17dB gain from the line stage) is
stable; how much feedback you can apply to lower the gain without stability problems
I donīt know. (I would estimate that the gain has to be > 3 at least).
seems I made a mistake in my question, I meant low gain + low feedback or high gain + high feedback. But you got he point.

Ciao

Paolo
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Old 15th March 2013, 05:03 PM   #382
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A 2SK246-2SJ103 combination would work OK for the JC-2 line stage.
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Old 15th March 2013, 08:22 PM   #383
pidigi is offline pidigi  Italy
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thank you John for chiming in!!


Quote:
Originally Posted by john curl View Post
A 2SK246-2SJ103 combination would work OK for the JC-2 line stage.
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Old 16th March 2013, 01:01 PM   #384
gk7 is offline gk7
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Thanks John, thatīs good to know.
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Georg
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Old 18th March 2013, 01:33 PM   #385
pidigi is offline pidigi  Italy
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I am trying to match the jfets (yes, I know that I can buy them already matched but I have some around that I would like to use), but I see that there can be a significant difference in Vgs between similar (<1%) Idss devices. In this particular application is better to closely match them for Idss or Vgs? ....or both?


Thanks,

Paolo
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Old 18th March 2013, 03:56 PM   #386
AndrewT is offline AndrewT  Scotland
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When Vgs = 0, then you have Idss.
In other words when you select two same Idss devices and bias them to that value of current then the Vgs MUST be the same for the two devices.

If you were to bias the two devices to a lower value current, Id, then you will have a Vgs for each device. Now it is quite likely that the Vgs will not be the same for the two selected devices at this lower Id.

The Vgs follows a slope when plotted against Id.
Matching the SLOPE of the Vgs between devices is what matching jFETs is about.

Selecting a pair, or a quad, of same Idss devices is not matching, even though some Members sell devices with the "matched" description attached.

If you intend to bias your jFETs at a different current value from the Idss, then you should be matching the slope of Vgs vs Id, if the circuit requires similar parameters for designed performance.
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Old 19th March 2013, 12:54 PM   #387
pidigi is offline pidigi  Italy
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Thanks Andrew.
What if I match them for Idss and Vgs? I mean, can this matching be considered like having matched them for Vgs vs Id slope?
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Old 19th March 2013, 12:59 PM   #388
pidigi is offline pidigi  Italy
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Georg, I have seen in your last version that you used a trimmer between the bases of the output transistor in order to set the offset. Is this the best solution? I am asking because I have seen somewhere that a trimmer in place of R2 has been used. Basically I agree with your solution, if a matched quad of jfets is used.
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Old 19th March 2013, 04:19 PM   #389
AndrewT is offline AndrewT  Scotland
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I don't think you understand what I have been posting.
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Old 19th March 2013, 06:00 PM   #390
pidigi is offline pidigi  Italy
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Andrew, maybe I don'understand or I didn't make myself clear. What I mean is that the relationship between Vgs and Id should be quite clearly defined, so if I have 2 devices with same Idss and Vt then the slope should be the same. Is it correct?
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