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Old 18th June 2010, 10:09 AM   #311
gk7 is offline gk7
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I have increased the output pairs from 2 to 3 and ommited the source
resistors which should give me (almost) 30mA.
Iīm not sure yet about the current source of the input stage. I would
like to have slightly more current but Iīm not aware of any higher
Idss FETs which have low noise at the same time.
Would any drawback result from using a bipolar current source instead ?
But probably itīs ok anyway...
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Old 18th June 2010, 10:35 AM   #312
AndrewT is offline AndrewT  Scotland
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CCS of two 2sk170v in parallel. Could probably put back in a 1r0 source resistor with trimmer to ensure current equalisation.

But why run the input jFETs at near 100% of Idss?
Would the k170 input pair perform just as well or better at 50% of Idss or even 30% of Idss?
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Old 18th June 2010, 11:25 AM   #313
gk7 is offline gk7
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Well thatīs what I thought, 50% will probably be ok, I used that before. The reason why I considered more current was post #290 where John said "The JC-2 phono input stage used Siliconix J110 input devices that are high current switches, that usually have an Idss of over 20 ma. The input devices were used at about 15 ma ea for lowest possible input noise. When you change the Id of the input devices in order to use lower Idss types, then you MUST change the load resistors, and this LOWERS the open loop bandwidth."
Lower open loop bandwidth certainly is not a good thing if we can avoid it (to some degree).
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Old 18th June 2010, 04:11 PM   #314
AndrewT is offline AndrewT  Scotland
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don't use lower Idss types.
Keep the same v graded, but run them at a lower bias than 100%.
What are the consequences?
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Old 18th June 2010, 04:32 PM   #315
gk7 is offline gk7
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I donīt want to use lower Idss types for the input stage and I donīt run them at 100%. As you can see from the schematic they are at 50% but maybe 70% or so would be preferable for the reasons given in post #290. The output stage FETs are BL and not V, not because I would not prefer V grade but because matched 2SK170V / 2SJ74V are not available any more, this was already discussed in posts #292 and #293.
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Old 19th June 2010, 09:35 AM   #316
Aneat is offline Aneat  China
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Default What the FFT figure meaning is ?

I find 1.5Khz appeared in FFT figure ,iuput were 1KHz.
That would be IM distortion frequency ?
But FFT should be harmonics ,it's right?
It' puzzles me.
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Old 20th June 2010, 12:49 AM   #317
Aneat is offline Aneat  China
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321# Click the image to open in full size.

When circuit simulation I find 1.5Khz appeared in FFT figure ,iuput were 1KHz.
That would be IM distortion frequency ?
But FFT should be harmonics ,it's right?
It's puzzles me.
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Old 21st June 2010, 04:34 PM   #318
gk7 is offline gk7
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The image you posted does not load (at least not on my computer).
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Old 21st June 2010, 07:40 PM   #319
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I think you guys are in the right ballpark. All else being equal, with this design, more Idss is better. Running at 50% of Idss or even to 80% is best, the jfet can still put out to more than 100% on dynamic peaks without anything obvious going on. However operating at 0 bias, or 100% is iffy.
The higher Idss part gives you a lower value load resistor that extends the open loop bandwidth. The higher percentage of Idss you bias, does the same thing.
However, a medium Idss part will work OK, if you don't starve it.
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Old 24th June 2010, 04:08 AM   #320
Aneat is offline Aneat  China
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Quote:
Originally Posted by gk7 View Post
The image you posted does not load (at least not on my computer).
My post is Chinese Net,
but I cannot post here ,because upload failure.
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