Mullard SS power amplifier

[jkeny]

I'm coming to this thread late mainly by searching for sliding bias topology. So my assumption is that this reworking of the original Mullard amp (brilliant work Lumanaw, LXG & Nordic) has retained this sliding bias topology!

I see this hasn't had activity since 7/2008 - has nobody built this? It looked to have so much potential!

What is the dissipation of the O/P devices - is it operating at a lower bias than full class A as is possible with sliding bias?

I hope there is a good outcome to this post as it seems a shame to let this one die!

[linuxguru]

Thanks - no, it's not dead by a long shot. There are two prototype PCB layouts on this thread, both started by Nordic. I was hoping somebody would take it from there, make a prototype and see how it sounded.

The dissipation depends on the rail voltage(s) and the quiescent current - at +/- 24V and 1.25 A, it's 60W dissipation per ch., but you can safely lower the rail voltages to as low as +/- 12 V, Icq=1A for approx. 6W per ch. output power into 8 ohms., with a dissipation of 24W/ch, Class-AB at max swings.

[jkeny]

Thanks LXG,
Are these not class-A dissipation ranges? What does the sliding bias do?

With those sort of exemplary THD figures the only question is how does it sound - you built some early prototypes, I think - what were your impressions?

Nordic, how did the prototype from the pics work out? And same question to you.

[jkeny]

Forgive my stupidity - it is a class-A amp so no surprise with the dissipation, doh!

[gannaji]

Dear all,
As I was browing the various threads, I stumbled on this thread and read it completely. I made notes on a paper about 40 years back and also copied the drawing. I copied the drawing into LTspice and my notes, what ever I could retrieve are as below. Hope this will be of interest!
I used to be very careful in making notes, but in this drawing, the circuit around Tr2 & 3 and Feed back is not clear to me. Please I want to understand the operation of this circuit as an exercise. Can any body who followed the scheme explain it a bit and show how the Power dissipation etc are derived?

Mullard 10 watt amplifier.
Normal Loading, Iq = 0.4 amps.
Low Loading, Iq = 0.27 amps.
Ripple < 100 mv.

Iq = Ipk/Pi and Pout = Icpk*Vcpk/2
Provided the load does not at any frequency fall below Rl = Vc/(Pi*Iq), crossover distortion cannot appear. With this particular method of class AB, (Pi mode AB), the collector dissipation is maximum under no drive conditions and Pc = Vc*Icpk/Pi which is nearly equal to 2/3 Pout (Max)
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The changeover from Class A to class AB operation occurs at 0.4*Pout max.
Overall Negative Feed Back of 44db is applied.
The Stability of the collector currents is ensured by direct coupling the phase splitter to the output stage and by over all negative DC feed back. Thus Iq through output transisters is defined by one Nfb loop and midpoint voltage by the other loop.
The normal collector dissipation of the output Transister = 9.2 watts/trans
Max Pc = (+30%) = 12.2 watts.
If Iq is reduced to 0.27 amps, 5 watts output for constant Sine wave drive.
Max dissipation = 8.3 watts.
Dissipation of OC 81 Z = 500 mw.
Dissipation of TR3 = 160 mw.
If the emitter Resistance, decoupled, is made large enough so that the DC is well defined, then the dynamic Bias condition of the transistor has to adjust itself with drive so as to maintain constant DC. Upto a certain power level, both the transistors operate in class A PP. Beyound this point, each transistor is cut off for part of the cycle. Also each transistor sees half the class A load during that part of the cycle during which its partner is cut off. As the drive is increased beyond this point, the total current will also tend to increase. The operating point will however shift so as to return the overall DC consumption to its previous value. With the increasing drive, the operation shifts to class B and then to class C conditions.
For audio amp applications, the design shold be such that the class B condition is reached at max power output. For this case, the Iq, Ipk, Vc & Rl are related by
Iq = Ipk/Pi = Vc/piRl, where Ipk is the peak current at max output, and Rl is the load seen by each collector independently. The design of the output stages is the same as for a Class B stage, delivering the same power but the ---
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