NPN vs PNP input stage

[Nelson Pass]

That would be Schroedinger's cat.

[Christer]

Originally posted by Nelson Pass
That would be Schroedinger's cat.

We're getting deeper and deeper into the physics.

[lumanauw]

BUT what about the drive for the second stage? Comp. Differential gives you almost perfect push-pull drive for the output stage. This criticism of the lack of perfect mirror image is lost in the advantage of one drive device turning on, while its complement is turning off from the opposite rail. This is invariably better as far as open loop distortion is concerned.

I understand that dual differential (complementary differential to some people) gives push-pull action in the VAS.
Single diffential lead us to single transistor VAS, with CCS on the other side (like Mr.Pass' designs, but not A75)

What's the real difference between push-pull VAS and single transistor VAS+CCS? Open loop distortion? Final sound characteristic?

[Nelson Pass]

There are several things to consider:

Dual diff input pairs driving complementary Common Emitter/
Source pairs does give lower distortion by higher open loop
gain and cancellation of 2nd harmonic.

Single diff pairs, with a single Common Emitter/Source device
gives very solid DC stability because it's anchored by a constant
current source (keeping in mind that the current through this
circuit helps set up the bias voltage for the output stage), has
about 6 dB less open loop, and higher 2nd harmonic content.

Take your pick.

[lumanauw]

Mr. Pass, I have looked at A75 paper again and again. In one part of the paper, the threshold voltage for N mosfet average=4.4V, while for P mosfet average=4V.

I looked at the sch of A75, you use IRF9510 and IRF610 for push-pull VAS. If the threshold of IRF9510 and IRF610 is quite different, will it be the total differential resistor (R6+P1 and R1+P2) will be different value? What happens if we do not use P to trim the resistors, will the differential+VAS working properly due to different threshold gate voltage?

[Nelson Pass]

Vgs varies quite a bit not only between different device types,
but also within device types, and by itself is no big deal. It
is accommodated by either selecting Vgs from a population
or trimming the values of resistors. Without trimming both
ends of the VAS stage of the A75, you will see improper bias
of that stage and DC offset at the output. That's just the way
it is.

[Jocko Homo]

Why does all the really good stuff happen when I am gone? Must be a conspiracy.

Anyway......another reason that some folks use PNP inputs is that it allows for a NPN in the second stage. The slightly lower capacitance (compared to the PNP compliment) will yield a higher unity gain frequency. Maybe not much, but sometime every little bit helps.

Jocko

[mandat]

PNP transistors have lower U(CE), too.