Hi.
I'm using Orcad Capture / PSpice and I'm going to simulate a circuit with some IRFP260N in parallel.
How do I model this with "non-perfect" mosfets? In real-life the mosfets won´t share the current equally and one fet will dissipate more than the others. Any ideas on how to model this?
How do i measure the relevant data if I want to match 3 mosfets for a relative "slow" application as a DC-load-module?
Regards TroelsM
I'm using Orcad Capture / PSpice and I'm going to simulate a circuit with some IRFP260N in parallel.
How do I model this with "non-perfect" mosfets? In real-life the mosfets won´t share the current equally and one fet will dissipate more than the others. Any ideas on how to model this?
How do i measure the relevant data if I want to match 3 mosfets for a relative "slow" application as a DC-load-module?
Regards TroelsM
Hi.
Thanks for the fast answer
Could you be a little more specific?
I'm planning on using a separate driver-opamp for each mosfet, but I'm still worried about the sharing.
I don't get the part about the shunt resistor? A shunt goes around something? - do you mean a source-resistor?
Regards TroelsM
Thanks for the fast answer
Could you be a little more specific?
I'm planning on using a separate driver-opamp for each mosfet, but I'm still worried about the sharing.
I don't get the part about the shunt resistor? A shunt goes around something? - do you mean a source-resistor?
Regards TroelsM
I think it would be pretty hard to figure out in what range the source-resistors should vary.
Actually I haven't got a clue how people get mosfets to share the current without matching them. Seems to be pretty hard.
I´ll press on with a design that controls each Mosfet individually to get a true current-sharing.
Regards TroelsM
Actually I haven't got a clue how people get mosfets to share the current without matching them. Seems to be pretty hard.
I´ll press on with a design that controls each Mosfet individually to get a true current-sharing.
Regards TroelsM
TroelsM said:
That's why amp designs with paralleled transistors in the output have small value source/emitter resistors. The resistors force the output transistors to share the current. The greater the resistance, the better the sharing, but the output Z rises too, so usually an attempt is made to match the output devices as closely as practical so the resistors can be kept small, helping keep the output Z low.
I_F
Yes I know and understand that the source-resistors help to share current but in a test-setup here on my desk i have two IRFP260N that "shares" in a 30/70 ratio with 0.5 ohm source-resistors.... That´s not very good.
So in a design where you need to be sure that one mosfet are not stressed much more than the others the source-resistors are no good.
That's why i asked if anyone knew how to simulate the difference in PSpice. I'm aware that it is no easy task, but someone might just have the answer anyway.
Regards TroelsM
So in a design where you need to be sure that one mosfet are not stressed much more than the others the source-resistors are no good.
That's why i asked if anyone knew how to simulate the difference in PSpice. I'm aware that it is no easy task, but someone might just have the answer anyway.
Regards TroelsM
I don't know if PSPICE supports it, but many spice simulators have a multiplier parameter m that you can add to the netlist.
Normally m gets integer values to represent multiple parts in parallel.
But I think maybe you can set m=1.05 or m=0.95 or something if your simulator supports it; this would represent a FET 105% stronger or 95% as strong, respectively.
By combining this with small ideal voltage sources in series with the gates to model threshold voltage mismatch, you can represent mismatch pretty well.
Normally m gets integer values to represent multiple parts in parallel.
But I think maybe you can set m=1.05 or m=0.95 or something if your simulator supports it; this would represent a FET 105% stronger or 95% as strong, respectively.
By combining this with small ideal voltage sources in series with the gates to model threshold voltage mismatch, you can represent mismatch pretty well.
TroelsM said:
You would need to match gate threshold voltages, but even then imbalance can result if one of the fets gets hotter. In some cases source resistors+matching alone can be enough, and in other cases you need invidual feedback for each mosfet, depending on your specs. Low-voltage high-current load is worst case (As you cant waste 2 volts on source resistors to balance if you are testing lets say 3.3v dc supply with 100A )
I would go for invidual control, no need to match gs-Vth for fets.
Much less will matter than in terms of matching.... all you need is a gate resistor.- Status
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