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Old 13th September 2011, 03:49 PM   #11
marce is offline marce  United Kingdom
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I miss the simpler boards, spent 8 years at a place and only got to 8 layers once (lots of soics and analogue, used imperial in thise days, and never thought I would change, wot a Luddite I was) , with SIV, length matching, having to use the interactive routers due to the complexities, the job has lost some of that relaxing feal that I use to get when routing. I still get to do the odd SMPS which I enjoy the most, as you can be quite creative with the copper, to try and keep EMC and all the other mush at bay. I'm lucky, we only go down to 0.8mm BGA's, I correspond with a couple of guys overseas that are ripping their hair out - 0.4mm pitch BGA's.
My mates just moved from here to a Manchester based mixing desk company and had to move to Pads, he's enjoying it, but would still prefer to be on good old Cadstar.

Just thought, you'll have access to all the 7351 stuff as Mentor bought Valour, who had bought PCB Libraries, who did a lot of the IPC-7351 stuff, and I believe Mentor are adding the tools to their products whilst doubling the price tio everyone else.

Last edited by marce; 13th September 2011 at 03:53 PM.
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Old 13th September 2011, 11:28 PM   #12
rjm is offline rjm  Japan
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Thanks to everyone who replied.

Alright, I'll give layout a re-spin starting from a 0.635mm grid. While my needs are far removed from the industrial applications being discussed later in this thread, going with metric from the ground up should solve a few of the nagging annoyances I ran into interfacing metric/imperial in past designs.

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Old 14th September 2011, 08:09 AM   #13
marce is offline marce  United Kingdom
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Old 14th September 2011, 10:12 AM   #14
marce is offline marce  United Kingdom
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Just for a bit of fun and info:
Its not often I use the 1.27mm pitch SOIC's these days, so I had to delve into an old design. These are 1.27mm SOIC's routed using the 0.05mm recommended grid. It is just for information, but as you can see It still looks neat, ie orthogonal tracks and 45 corners. With most EDA packages if you start the route from the pad it will put the first via or corner on a grid point that centres on the pad and on the 0.05mm grid. If you did it the other way the track would be slightly of centre of the pad, but still be acceptable.
To show the contrast between SOIC's and some of today's components, the second picture shows a 16pin SOIC next to a bit of a DDR memory interface, the ball pitch is 0.1mm in the X and 0.8mm in the Y axis. The actual pads for the BGA are smaller than the vias (light green with grey drill hole), the finished hole size for the vias is 0.25mm, track and gap is 0.1/0.1mm. This is standard geometry these days with PC's etc, the next generation HDI gets even funkier.
http://www.pshk.org.hk/Activity%20DO...020.2.2009.pdf
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File Type: png SOIC-mm-grid.png (64.8 KB, 40 views)
File Type: png SOIC-with DDR.png (21.2 KB, 40 views)
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Old 14th September 2011, 11:36 AM   #15
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Do the design rules of your company require the PCBs to have one test point (for the ICT) per node? We have to do this (and use two test points per node for resistors of less than 22R). This really is a huge burden when trying to get high density. We are not allowed to use via holes as test points either.
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Old 14th September 2011, 12:02 PM   #16
marce is offline marce  United Kingdom
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We use boundry scan, then where required we add the minimum amount of testpoints (well actually use Preditors Testpoint function to add the testpoints or mark vias as suitable probing points). The board with the DDR memory is 86 sq cm, has 3500 pads and 2300 connections, we just couldn't get the test points on or get a jig made that would allow us to probe all the points.
Its 2000 since I last did a board where the engineer wanted test points on every node (and on a 0.1inch grid), they were a pain as he wouldn't let us use vias. When the cost of testing the boards started to outweigh the cost of the product he was finaly made to change. Basicly we do functional circuit test (JTAG, boundry scan) both here (tactical communications and surveillance) and my last place of work, and have had no problems. It is the trend theses days as getting the nodes on a design with so many small components and lack of space is couter productive both in finding problems and cost.
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Old 26th September 2011, 01:15 PM   #17
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For through hole it is probably best to just stick to Imperial. That way you are dealing with nice round numbers for spacing etc. while doing the layout. You can always change to Metric at the end.
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Old 30th September 2011, 11:29 AM   #18
marce is offline marce  United Kingdom
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Why, ISO standard measurement system is metric, once you enter your grid its all in the background.
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