Dear everyone, i am new to PCB making, and i am interested in designing a compact SMDs dac for siblings and my girlfriend. I have downloaded a free version diptrace, and my goal is :
-A USB power, i2s out, upsampling, and a WM8741/WM8742.
-Dual layer PCB, no fancy caps, fully smds.
However, i am in the trouble for finding the chips in the diptrace when i started to draw the schematic. Suppose a PCM2707 is using TQFP-32, but i just can't get it find by by entering such keywords under TI.
Any others keywords to be search?
A simple guide needed to the way of searching for different chips model in DIP-Trace. utmost appreciate with any helping hand.
-A USB power, i2s out, upsampling, and a WM8741/WM8742.
-Dual layer PCB, no fancy caps, fully smds.
However, i am in the trouble for finding the chips in the diptrace when i started to draw the schematic. Suppose a PCM2707 is using TQFP-32, but i just can't get it find by by entering such keywords under TI.
Any others keywords to be search? A simple guide needed to the way of searching for different chips model in DIP-Trace. utmost appreciate with any helping hand.
The package mechanical details and the reccomended footprint to IPC-7351 standard. The IPC-7351 standard for PCB footprints covers nearly all PCB required footprints, I'd say that anyone doing SMD PCB design should follow this standard, if for no other reason that th work has been done for you.
My only comment I'd make initialy can you go to a 4 layer PCB, this will be much easier to lay out and more criticaly better for signal integrity.
I would also recomend using a metric grid (0.05mm) and layout. Have a look for a document "The Cad library of the Future" by Tom Hausherr.
My only comment I'd make initialy can you go to a 4 layer PCB, this will be much easier to lay out and more criticaly better for signal integrity.
I would also recomend using a metric grid (0.05mm) and layout. Have a look for a document "The Cad library of the Future" by Tom Hausherr.
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Also in the free version of Diptrace the 250 pin limit is restrictive. I find if you use individual pads for as many components as you can rather than actual part outlines then you can go over that limit. I use the part initially for pin spacing etc, then match a pad size to it and drag them in place manually if I go over the limit.
Having looked at some of my stuff, a double sided layout would be possible (though not easy), but careful attention will be required to ensure you achieve as near as possible a contiguous ground plane on the bottom of the board.
You have picked some fine pitch devices for a first off PCB design. The Wolfson devices at 0.65mm pitch can be very problematic to solder without solder resist between the pins (shorts). And all the integrated packages are prone to coplanarity problems which can lead to bad joints, so a flat finish (not HASL) will be required for the pads.
SMT HANDBOOK - QUALITY ISSUES
Wolson Footprints atached.
I use Cadstar or Allegro, but always the schematic comes first then this is transferred to the PCB directly. Any subsequent changes are done on the scheamtic and ECOed to the PCB. So that the PCB always matches the schematic.
You have picked some fine pitch devices for a first off PCB design. The Wolfson devices at 0.65mm pitch can be very problematic to solder without solder resist between the pins (shorts). And all the integrated packages are prone to coplanarity problems which can lead to bad joints, so a flat finish (not HASL) will be required for the pads.
SMT HANDBOOK - QUALITY ISSUES
Wolson Footprints atached.
I use Cadstar or Allegro, but always the schematic comes first then this is transferred to the PCB directly. Any subsequent changes are done on the scheamtic and ECOed to the PCB. So that the PCB always matches the schematic.
Thanks marce,
I just finish drawing the layout for the PCM2707 using component editor and attached to FQFP-32/5X5A. "I am kinda worry the footprint matching by the way"
The last step, where can i search for the spice model for this chip?
I just finish drawing the layout for the PCM2707 using component editor and attached to FQFP-32/5X5A. "I am kinda worry the footprint matching by the way"
An externally hosted image should be here but it was not working when we last tested it.
The last step, where can i search for the spice model for this chip?
Downloaded Diptrace and started having a little play, only with the Pattern Editor. First view is its a nice little program.
The footprint you require for the PCM2707 is the QFP-32/7x7/x1.65.
The 7x7 refers to the package dimensions 7mm square, the 1.65 is the height, and 32 is the number of pins.
The attached bit map is a screen shot from the Pattern Editor, the grid is set at 0.4mm and I've added a quick dimension to give an idea of the size.
From my initial look at the libraries that come with the package I've got to say I'm impressed with them, they look to be based on IPC-7351 standards.
The footprint you require for the PCM2707 is the QFP-32/7x7/x1.65.
The 7x7 refers to the package dimensions 7mm square, the 1.65 is the height, and 32 is the number of pins.
The attached bit map is a screen shot from the Pattern Editor, the grid is set at 0.4mm and I've added a quick dimension to give an idea of the size.
From my initial look at the libraries that come with the package I've got to say I'm impressed with them, they look to be based on IPC-7351 standards.
Attachments
Thanks guys for the help.
I just finished the i2s part drawing.
However, i am seeking for more advance drawing. The question is, How/what i need to set if i wish to mount the chips and smds parts at top and the bottom of the PCB? I would like to use both of the surface to mount all of the things. The reason is because i want to minimize any possible size.
I just finished the i2s part drawing.
An externally hosted image should be here but it was not working when we last tested it.
However, i am seeking for more advance drawing. The question is, How/what i need to set if i wish to mount the chips and smds parts at top and the bottom of the PCB? I would like to use both of the surface to mount all of the things. The reason is because i want to minimize any possible size.
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There are some problems with the layout, though without the schematic I can only point the first couple that are obvious and quite serious.
1: The input from the Xtal snakes all round the board, this is (after ground connections) the most important connection, it needs to be as short as possible and also any related capacitors should be placed near the crystal and the crystal placed next to pin 12 & 13 of the chip.
2: This type of design requires preferably a contigous ground plane on 1 side of the board, or copper pours stitched together with many via's. For a two layer device the components need to be layed out to minimise the ammount of routes that have to be dropped to the other side, allowing for max ground.
The way you have done the ground will cause EMI/EMC problems, and signal integrity problems.
Sorry to be so negative but at the moment IMO if the design works it will be plauged by EMC problems.
I would re-position the components, trying to minimise connection lengths, and as stated earlier minimise the ammount of routes that have to go on the reverse side. Decoupling capacitors placed near the device power pins. The crystal very near pins 12 & 13.
Double sided placement is possible with a two layer board, but better results are achieved by using a 4 layer board.
1: The input from the Xtal snakes all round the board, this is (after ground connections) the most important connection, it needs to be as short as possible and also any related capacitors should be placed near the crystal and the crystal placed next to pin 12 & 13 of the chip.
2: This type of design requires preferably a contigous ground plane on 1 side of the board, or copper pours stitched together with many via's. For a two layer device the components need to be layed out to minimise the ammount of routes that have to be dropped to the other side, allowing for max ground.
The way you have done the ground will cause EMI/EMC problems, and signal integrity problems.
Sorry to be so negative but at the moment IMO if the design works it will be plauged by EMC problems.
I would re-position the components, trying to minimise connection lengths, and as stated earlier minimise the ammount of routes that have to go on the reverse side. Decoupling capacitors placed near the device power pins. The crystal very near pins 12 & 13.
Double sided placement is possible with a two layer board, but better results are achieved by using a 4 layer board.
Hi Chchyong89,
I dont know whether you have taken umbrage with my comments regarding you layout, but PCB layout is critical to a circuit functioning correctly.
I invested several hours of my own time to re-search and provide some answers to your questions, including looking at Diptrace, this I did freely to help
a fellow DIYer.
And agian it was in this spirit that I looked at your layout, and what became immediatly apparent was some critical concerns with the circuit topography.
To re-iterate what I said about clock circuit layout I have attached a few application notes for your referance, regarding the critical layout requirements of crytal circuits.
The comments I made are to help you achieve you desired goal with this design, not to upset
http://www.latticesemi.com/documents/an8080.pdf
http://www.atmel.com/dyn/resources/prod_documents/doc8128.pdf
Page 9 in the following app note:
http://focus.ti.com/lit/an/sdya011/sdya011.pdf
I dont know whether you have taken umbrage with my comments regarding you layout, but PCB layout is critical to a circuit functioning correctly.
I invested several hours of my own time to re-search and provide some answers to your questions, including looking at Diptrace, this I did freely to help
a fellow DIYer.
And agian it was in this spirit that I looked at your layout, and what became immediatly apparent was some critical concerns with the circuit topography.
To re-iterate what I said about clock circuit layout I have attached a few application notes for your referance, regarding the critical layout requirements of crytal circuits.
The comments I made are to help you achieve you desired goal with this design, not to upset
http://www.latticesemi.com/documents/an8080.pdf
http://www.atmel.com/dyn/resources/prod_documents/doc8128.pdf
Page 9 in the following app note:
http://focus.ti.com/lit/an/sdya011/sdya011.pdf
Hi,
No hard feeling here, i am still on the way to learn as much as i can. And i really appreciate every of your comments. The more you guys point out my mistakes, the faster i can improve to have a better skill ain't it
However i am still drawing and redrawing the circuit before i show up myself here
Regards.
No hard feeling here, i am still on the way to learn as much as i can. And i really appreciate every of your comments. The more you guys point out my mistakes, the faster i can improve to have a better skill ain't it
However i am still drawing and redrawing the circuit before i show up myself here
Regards.
I've been doing PCB's as a job for 25 years, and I still make mistakes. I'm doing a layout of a class D, and the first pass at it I just dove in and threw it together. When I re-read the data sheets etc I realised I'd made a complete mess of it. So I started again, and the second time was much happier with the layout.
The Wolfson site has some good evaluation board layouts that are worth looking at, though not the same devices, the general priciples of how they are layed out will give you some idea of what you are aiming for.
The manual for this board is a good example. There is also a good layout example on this site using the same chip with a Nat chipamp layout as well, I cant find the link for that at the moment.
Evaluation Boards | WM8761EV1 | Wolfson Microelectronics
This site is a good intro to the basics of PCB design and worth a look at as well.
How to be a Circuit Board Designer
Keep playing with the component layouts, the trick is ti look at the patterns the connections make, after a while you begin to picture where the routes will go.
Marc
The Wolfson site has some good evaluation board layouts that are worth looking at, though not the same devices, the general priciples of how they are layed out will give you some idea of what you are aiming for.
The manual for this board is a good example. There is also a good layout example on this site using the same chip with a Nat chipamp layout as well, I cant find the link for that at the moment.
Evaluation Boards | WM8761EV1 | Wolfson Microelectronics
This site is a good intro to the basics of PCB design and worth a look at as well.
How to be a Circuit Board Designer
Keep playing with the component layouts, the trick is ti look at the patterns the connections make, after a while you begin to picture where the routes will go.
Marc
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