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Old 23rd July 2008, 11:06 AM   #681
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Quote:
Originally posted by lineup


Yes, I am aware of this.
And just because a spice file is called xxxxxx.sp3
it may very well have a level 1 model and not LEVEL 3

So, Edmond
you use only LEVEL 3 models?
I guess not ....
the SP3 file is a SPICE 3 file, not neccesarily a LEVEL 3 model. however, since SPICE models are usually text files, most manufacturer models state what LEVEL model they are in a comments section. not all of them do.
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Old 23rd July 2008, 11:40 AM   #682
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Quote:
Originally posted by lineup
.............
So, Edmond
you use only LEVEL 3 models?
I guess not ....
As for MOSFETs I'm using BSIM-V3.3 (level=8) or EKV models (level=44)

Cheers,
Edmond.
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Old 23rd July 2008, 11:59 AM   #683
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Quote:
Originally posted by Edmond Stuart
Hi John,

Indeed, we use different approaches. These are not only based on our preferences, but also on our circumstances. You have many lab resources and I have (after my retirement) plenty of time and far less lab equipment (only the basic stuff like scopes, signal generators and a distortion analyzer). But that's not all: I really hate designing PCBs, not to mention possible wiring or design errors. Therefore, in an attempt to avoid a (costly) PCB redesign, I'm using a simulator to detect possible errors in an early stage.

This approach will not always shorten the design cycle. As for my latest design (PCP amp), it takes a lot of time, by now, six month. Apart from convergence errors, the problem with this complex design is that, after each modification, one has to check not only things like distortion, bias current, PSRR, overload recovery, etc., but also all possible sources of instability: Miller loops, (global) NFB loops, CMCL's etc. (including loops in the regulated PSUs!)

In this regard I've learned from the PGP project: An early version started oscillating when the output exceeded a certain level (20V or so). The simulator did not reveal this. But if I had looked a bit closer, I should have discovered that indeed something was wrong: the phase margin of the Miller loop (around the VAS) was dangerous low, only 20 deg.

Anyhow, one thing is for sure: in the final end one has to build the thing in order to put in the final tweaks (and listen!)

Cheers,
Edmond.
Edmond,

All so very true.

WRT your PCP amp, can you tell us what are the design goals?

cheers

Terry
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Old 23rd July 2008, 01:05 PM   #684
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Default PCP

Quote:
Originally posted by Terry Demol
Edmond,

All so very true.

WRT your PCP amp, can you tell us what are the design goals?

cheers

Terry
Hi Terry,

The design goals are similar to those for the PGP amp, 200W into 4Ohm and THD20 < 1ppm. However, the architecture is quite different. NFB instead of EC applied to the output stage, TTMC instead of NDFL and four pair of vertical MOSFETs instead of three lateral pairs as output devices. Also auto-bias and over-current protection. It comprises about 70! trannies, hence its name: Pretty Complex Power amp.

For some precursors, see my website: http://home.tiscali.nl/data.odyssey/PMP.html

Cheers,
Edmond.
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Old 24th July 2008, 12:35 AM   #685
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Default Re: PCP

Quote:
Originally posted by Edmond Stuart


Hi Terry,

The design goals are similar to those for the PGP amp, 200W into 4Ohm and THD20 < 1ppm. However, the architecture is quite different. NFB instead of EC applied to the output stage, TTMC instead of NDFL and four pair of vertical MOSFETs instead of three lateral pairs as output devices. Also auto-bias and over-current protection. It comprises about 70! trannies, hence its name: Pretty Complex Power amp.

For some precursors, see my website: http://home.tiscali.nl/data.odyssey/PMP.html

Cheers,
Edmond.
Hi Edmond,

I look forward to seeing it, I am sure there will be some surprises
for us. Your last project was astounding.

It appears pcp will be more comfortable with difficult loads.

OK, apologies for slight subject shift - back to spice.

Cheers

Terry
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Old 24th July 2008, 02:13 AM   #686
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Default Re: Re: PCP

Quote:
Originally posted by Terry Demol

Hi Edmond,

Your last project was astounding.
[OT]

[/OT]
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Old 24th July 2008, 04:48 PM   #687
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Quote:
Originally posted by Edmond Stuart


As for MOSFETs I'm using BSIM-V3.3 (level=8) or EKV models (level=44)

Cheers,
Edmond.

Edmond and Andy_c,

I've also done some poking around with actual vertical power MOSFET measurements at low drain currents (10 mA to 1.5A) and found that the Level 1 SPICE models do not reflect the Id vs Vgs performance well in this region. And it does indeed seem true that the wingspan simulation of a Class AB MOSFET output stage is much worse as a result of the simple square law model in SPICE. Same for THD level and spectra.

Transconductance as a function of drain current for the square law model is just way off the mark. The exponential behavior of Id vs Vgs in the low-current region, and the transition to the square-law behavior, needs to be properly modeled, else one gets pessimistic distortion simulations. Waht did surprize me was that the area of inaccuracy of the simple SPICE model seems to be in a current region for vertical MOSFETs that is well above what we would normally think of as the threshold voltage. In other words, this "sub-threshold" behavior and region seems to extend further above threshold than I would have thought. Significant modeling error of Id vs Vgs and gm vs Ids seems to exist in the region of Id extending to a couple hundred mA. Have you guys noticed this?


It seems to me it would be REALLY nice if the LTspice VDMOS model supported the BSIM3 model for its DC part. I don't believe it does, however.

I don't think I've had too much luck with the EKV models in LTspice, but the BSIM3 may work better. Do either of you guys have a procedure for making up a BSIM3 model given measured Id vs Vgs data. What has your experience been in this regard? My familiarity with BSIM3 models is limited. All I really care about at this point is getting a much better fit of Id vs Vgs to the real-world behavior of real vertical MOSFETs.

Cheers,
Bob
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Old 24th July 2008, 05:58 PM   #688
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Hi Bob,

I don't have a BSIM extraction procedure.

You might try out the EKV models for the IRFP244 and FQA9P25. I've been using them for a while without trouble. I fixed these up after I found the problem that caused convergence errors in the Toshiba models. I haven't gone back and fixed the Toshiba MOSFET models.

These IRF and Fairchild models can be found starting here.
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Old 24th July 2008, 10:05 PM   #689
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Quote:
Originally posted by andy_c
Hi Bob,

I don't have a BSIM extraction procedure.

You might try out the EKV models for the IRFP244 and FQA9P25. I've been using them for a while without trouble. I fixed these up after I found the problem that caused convergence errors in the Toshiba models. I haven't gone back and fixed the Toshiba MOSFET models.

These IRF and Fairchild models can be found starting here.

Thanks, I'll give it a shot.

Bob
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Old 25th July 2008, 04:22 AM   #690
1audio is online now 1audio  United States
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I have used these models in the past with LTspice and they seemed to work: Supertex They didn't crash or fail to converge and the biases were pretty close to the real parts in a PCB. I'm not sure just how precise they are. however this class of devices are rarely used for linear applications so the precision of the transfer curve is secondary to the modeling of the charges when switching the device on and off, at least for their target customers.
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